ECE 3561 - Advanced Digital Design
Au 2016 - MWF 1:50-2:45pm Journalism 300
Final Exam : Wed Dec 14, 2016 2:00-3:45pm in classroom
Course Syllabus : ECE3561/Syllabus/Syllabus3561 Adv Dig Dsgn - Au16.doc
Material Covered :
Lectures (below) - Assignments (Assignments)
Lectures :
1W - 1. Course Intro - ECE 3561 - Lecture 01.ppt Lecture 01.pdf
1F - 2. Sequential Deisgn Basics - ECE 3561 - Lecture 02.ppt (Quiz 1) Lecture 02.pdf
2M - 3. Common Elements - ECE3561/Lectures/ECE 3561 - Lecture 03.ppt Lecture 03.pdf
2W - 4. Traditional Seq Circ Dsgn - L5 Seq Circuit Design Traditional.ppt Lecture 5 .pdf
2F - 5. State Graphs and Tables (Quiz 2) - L6 State Graphs and Tables.ppt Lecture 6.pdf
3M - Labor Day - (Sept 5) no class
3W - 6. Moore Machines L7 State Graphs and Tables - Moore Machines.ppt
L7 State Graphs and Tables - Moore Machines.pdf
3F - ARPA Briefing 1:00 to 2;00 : Class start late - Material review (optional class)
4M - 7. (Sep 12) Multiple Output Example - - L 7s - Multiple Output Example.ppt
Lecture 7s - Multiple Output Example.pdf
4W - (Quiz 3) L8 - State Reduction : L 8 State Reduction.ppt Lecture 8 State Reduction.pdf
4F - L9 - State Assignment : L 9 State Assignment.ppt Lecture 9 State Assignment.pdf
5M - L10 - State Machine Topics Z: L 10 State Machine Design Topics.ppt
Lecture 10 State Machine Design Topics.pdf
5W - NO CLASS to allow students to attend career fair
5F - Additional equivalence and one hot : L10a additional State Machine examples.ppt
Lecture 10a additional State Machine examples.pdf
6M - State Machine Timing and analysis : ECE 3561 - Lecture 11 State Machine Analysis.ppt
6W - Problem Session / (Quiz 4)
6F - Exam Review ECE 3561 - Lecture 11 Midterm Review.ppt
7M (Oct 3rd) MIDTERM EXAM
7W VHDL Overview : ECE 3561 - Lecture 12 VHDL Overview.ppt
7F Class canceled
8M VHDL Language Elements I : ECE 3561 - Lecture 13 VHDL Language Elements.ppt
8W - No class - at NSF
FALL BREAK
9M VHDL Language Elements 2 : ECE 3561 - Lecture 14 VHDL Language Elements II.ppt
9W VHDL and state machines : ECE 3561 - Lecture 15 VHDL Specification of State Machines.ppt
9F Testing of state machines : ECE 3561 - Lecture 16 VHDL Testbenches for State Machines.ppt
(Quiz 5)
10M - NO CLASS due to travel
10W State machines with binary encoding of states : ECE 3561 - Lecture 17 VHDL for State Machines with binary state encoding.ppt
11F Demo of modelsim and Quartis
12M No Class due to doctors appointment
12W Other counters - microbaby components
12F Quartis synthesis and assignments
Lect and files Lecture 2x Microbaby Structure.ppt Lecture 25 Datapath ALU.ppt Lecture 26 Datapath ALU Structure and generation.ppt MicroBaby Datapath Creation.ppt
FINAL REVIEW : ECE 3561 - Lecture 30 Final review.ppt
L2 : NTI: Read Unit 11 / Prob 11.1 / Unit 11 Study Guide / REVIEW basic combination logic design U 5,7,8,9
L4 : Read the article in this month's IEEE Spectrum "The Surprising Story of the First Microprocessors" and write a 1 to 2 page report on the article. Submit to drop box. DUE : Sept 8
L6 : Look at prob 14.4 thru 14.11 - answers in text // 14.14 a) and b) - Turn into drop box DUE: Monday Sept 12th
4W L8 : Go over prob 14.4 through 14.11 - bring questions to class #12 - NTI : probs 15.1a,2,10a
VHDL Assign 1 : VHDL Assign 1.doc DUE: Friday Oct 21
VHDL Assign 2 : VHDL Assign 2 2016.doc DUE: Friday Oct 28
MB Assign 1 : MB Assign 1.docx DUE: Friday Nov 11
MB Assign 2 : MB Assign 2.docx DUE : Tuesday Nov 22
MB Assign 3 : MB Assign 3 2016.docx Due : Tuesday Nov 22 testbench AU16 HDL Code/tbadd.vhdl
MB Assign 4 : MB Assign 4.docx DUE : Friday Dec 2 testbench AU16 HDL Code/tbalu.vhdl
files: fa.vhdl mux2t1.vhdl mux2t1x4.vhdl mux2t1x8.vhdl mux4t1.vhdl
MB Assign 5 : MB Assign 5.docx DUE : Wed Dec 7 testbench v1 : dptb.vhdl
A reference alu and its files add4.vhdl mux2t1x4.vhdl mux2t1.vhdl csa8.vhdl lu8.vhdl mux4t1.vhdl
mux2t1x8.vhdl alu.vhdl all0s.vhdl
Code for an ALU - coming soon