LIBRARY IEEE;
USE ieee.std_logic_1164.all;

ENTITY tbadd IS
END tbadd;

ARCHITECTURE one OF tbadd IS
  --declare the ripple carry adder
  COMPONENT add8 IS
     PORT (A,B : IN std_logic_vector (7 downto 0);
           Cin : IN std_logic;
           Sum : OUT std_logic_vector (7 downto 0);
           Cout : OUT std_logic);
  END COMPONENT;
  FOR all : add8 USE ENTITY work.add8(one);
  -------------------------------
  COMPONENT csa8 IS
    PORT (A,B : IN std_logic_vector (7 downto 0);
          Cin : IN std_logic;
          Sum : OUT std_logic_vector (7 downto 0);
          Cout : OUT std_logic);
  END COMPONENT;
  FOR all : csa8 USE ENTITY work.csa8(one);
  --declare local signals
  SIGNAL A,B,Sum_rip : std_logic_vector (7 downto 0);
  SIGNAL Cin,Cout_rip,Cout_csa : std_logic;
  SIGNAL Sum_csa : std_logic_vector (7 downto 0);


BEGIN
  --instantiate ccmponent
  urip : add8 PORT MAP (A,B,Cin,Sum_rip,Cout_rip);
  ucsa : csa8 PORT MAP (A,B,Cin,Sum_csa,Cout_csa);
  
   PROCESS
   BEGIN
     Cin <= '0';
     FOR i IN 0 to 1 Loop
     A <= "00000000";   B <= "00000000";
     WAIT FOR 50 ns;
     A <= "11111111";   B <= "00000001";
     WAIT FOR 50 ns;
      A <= "00000000";   B <= "11111111";
     WAIT FOR 50 ns;
     A <= "11101111";   B <= "00010001";
     WAIT FOR 50 ns;    
     A <= "01010101";   B <= "10101010";
     WAIT FOR 50 ns;
     A <= "00001111";   B <= "11110010";
     WAIT FOR 50 ns;
     Cin <= '1'; WAIT FOR 50 ns;
     END Loop;
     WAIT;
   END PROCESS;



END one;