The Cadence® toolset is a complete Integrated Circuit (IC) Electronic Design Automation (EDA) system used to devlop commercial analog, digital, mixed-signal and RF ICs and circuit boards. The toolset is utilized in in the Department of Electrical and Computer Engineering at The Ohio State University throughout the analog/mixed signal courses and is employed to create state-of-the art circuits in research labs.
ECE 4021 Analog Integrated Circuits I (Custom IC)
ECE 5020 Mixed Signal VLSI (Custom IC, Digital IC)
ECE 5021 Analog Integrated Circuits II (Custom IC)
ECE 5022 Radio Frequency Integrated Circuits (Custom IC)
ECE 5227 Fundamentals of Power Management Integrated Circuits for VLSI Systems (Custom IC, Verification)
ECE 7020 Integrated Circuit Design of Data Converters and Phase-Locked Loops (Custom IC, Verification)
ECE 7027 Advanced Topics in Analog VLSI Design (Custom IC, Verification)
ECE 7022 Advanced RF Integrated Circuits (Custom IC, Verification)
ECE 7821 Mixed Signal Verification and CAD Tools (Custom IC)
Information Electronics Research Group
The Cadence tools installed on the ECE machines at The Ohio State University are the same as those at most professional mixed-signal microelectronics company in the United States. These tools are used for transitor-level analog design, spice level simulation (using spectre), transistor-level layout, as well as parasitic extraction (resistive and capacitive) on a post-layout design. This design flow encompases the major portion of any IC design effort. The tools are also capable of implementing a multi-million gate digital design flow, including simulation, synthesis, and physically-knowledgable place and route. Finally, the tools integrate with other EM solvers, simulators, and verification engines to provide design capability right up through multi-GHz RF.
For each silicon process node (ie. 0.5um, 0.18um, 90nm ...) the toolset is configured via a foundry provided design kit or process design kit (PDK). This kit contains schematic symbols, simulation models, programmable layout cells (PCELLs) and verification routines for design objects available in the process node. For example, a PDK would contain schematic symbols for transistors, capacitors, and resistors available in a given technology node. It would also contain simulation models for the transistors, capacitors, and resistors that are parameterized based on physical attributes such as length and width. Simulations of a design are run by placing the symbols onto a schematic, parameterizing them appropriate to the desired function and instantiating stimulus for the design. Some PDKs allow the parameters from design schematics to be propigated to the layout, automatically sizing design elements. Verification routines check for layout rule compliance (DRC) and extract design element sizes from a layout for validation that the layout matches the schematic (LVS).
Note that without a foundry-provided design kit, no designcan be done. Hence, provided below are instructions on how to setup an OSU ECE account for using Cadence tools, then below that are instructions on how to set up an IBM PDK, then below that are instructions on how to set up an AMS PDK and a Cadence simulations tutorial.
Also, we strongly recommend using the directory structures/names presented in the Cadence setup instructions below. Further, do not run Virtuoso in your root directory; the files that are created by one design kit can interfere with other ones.
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Information is provided 'as is' without warranty of any kind. No statement is made and no attempt has been made to examine the information, either with respect to operability, origin, authorship, or otherwise. Please use this information at your own risk. We recommend using it on a copy of your data to be sure you understand what it does under your conditions. Keep your master intact until you are satisfied with the use of this information within your environment.
Cadence is a registered trademark of Cadence Design Systems, Inc., 2655 Seely Avenue, San Jose, CA 95134.Updated by Ayman Fayed, December 22, 2017