Hardware Description Languages
WINTER 2012 Assignments: Asgn
Lectures (WI 2012) (update in progress 1/3/2011)
W1: Lecture 1 - Course Introduction - ee762/LectWI09/L1 - Course Intro.ppt
F1: Lecture 2 - VHDL Introduction - ee762/LectWI09/Lect 2 - VHDL Introduction.ppt
HW 1 - Introduction to Modelsim ee762/Assign_2011/HW 1 WI11.doc due Mon Jan 10, 2011
M2: Lecture 3 - Data Paths - Lect 3 - Data Paths 1.ppt
M2: Project Step 1 - Lect 3 - Project Step 1.ppt
W2: Lecture 4 - Data Paths 2 - Lect 4 - Data Paths 2.ppt
F2: Project Step 2 - Lect 5 - Project Step 2.ppt due Wed Jan 19, 2011
M3: Holiday
W3: Lecture 6 - Lect 6 - Language Overview I.ppt
F3: Project Step 3 - Lect 7 - Project Step 3.ppt due Wed Jan 26, 2011
Lecture 7 - Lect 7 - Language Overview II.ppt
M4: Finish Language Overview II
Lecture 8 - Lect 8 - Language Overview III.ppt
W4: Continue with Lect 8
Project Step 4 - Lect 9 - Project Step 4.ppt
F4: Finish Lang Ov III
M5: Lecture 10 - Lect 10 - Attributes.ppt Proj 4 due.
Project Step 5 Lect 11 - Project Step 5.ppt
W5: Timing and Currency - Lect 12 - Timing & Concurrency I.ppt
F5: Timing and Currency cont.
M6: Exam Review Midterm Exam Review.ppt
Project Step 6 - Lect 15 - Project Step 6.ppt and review of project steps 1 through 5
W6: MIDTERM EXAM
F6: Timing and Concurrency II - Lect 15 - Timing & Concurrency II.ppt
M7: Resolved Signals - Lect 17 - Resolved Signals.ppt
Project Step 7 - Registers - Lect 18 - Project Step 7.ppt
W7: Timing and Concurrency III - WI09/Lect 16 - Timing & Concurrency III.ppt
F7: Finish Timing an Concurrency III
A complete datapath - Project Step 8 - Lect 20 - Project Step 8.ppt
M8: Complete material in Timing and Concurrency III
EXTRA CREDIT : Lect 23 - Project Step Extra Credit.ppt
W8: Project Step 9 - A successive approximation A to D Lect 23 - Project Step 9.ppt
State Machine Descriptions - Lect 22 -State Machine Design.ppt
F8: Go over new material in Lect 22 and update on PS 9
UPDATED Marker
M9: At DVCON - Traveling - NO Class but material to be reviewed
W9: At DVCON - NO Class
F9: Project Step 10 - Floating Point Adder Lect 25 - Project Step 10.ppt
IEEE Floating Point Lect 24 -IEEE Floating Point Units.ppt
Extra Credit Project Step Announced
M10: Lect 26 -IEEE Floating Point Adder Arch.ppt
W10: Lect 27 - Verilog Intro.ppt
F10: Final Exam Review
FINAL EXAM : Final Exams period - on syllabus.
Package STD1164_LOGIC std_1164.vhd
NOTE: Waveforms are to be submitted as .pdf or .bit files. On the LINUX systems the command to do that is ps2pdf and you can man ps2pdf to get the details. On the PCs, having Modelsim running and the waveform window as the active window, you can choose export from the pulldown menu to output a .bit file, or choose print and select .pdf as the printer and check the print to file. USE THE .do files provided!!
ps2pdf man page - ee762/info_ps2pdf
HW1: Due Monday Jan 10: ee762/Assgn 2010/HW 1.doc
PS1: Due Friday Jan 14: PS1.doc pr_step1.vhdl
PS2: Due Wednesday Jan 19: PS2.doc pr_step2.vhdl
PS3: Due Wednesday Jan 26: PS3.doc pr_step3.vhdl ps3_list.do ps3_wave.do
PS4: Due Monday Jan 31: PS4.doc pr_step4.vhdl p4_list.do p4_wave.do
PS5: Due Friday Feb 4 PS5.doc pr_step5.vhdl p5_list.do p5_wave.do
PS6: Due Monday Feb 14: PS6.doc pr_step6.vhdl ps6_list.do ps6_wave.do
PS7: Due Friday FeB 18: PS7.doc pr_step7.vhdl ps7_list.do ps7_wave.do
PS8: Due Wednesday Feb 23 PS8.doc pr_step8.vhdl ps8_list.do ps8_wave.do
PS9: Due Monday Mar 7: PSsar.doc sar_tb.vhdl pssar_list.do pssar_wave.do
EXTRA CREDIT: pr_step_excr.vhdl excr_list.do excr_wave.do
Description ee762\PS Extra Credit.htm
and start with your code and package from step 8
UPDATED Marker ^^
PS10: Due Monday Mar 16 - PS10.doc: fpm_your_model.vhdl fpmtb.vhdl fpm_list.do fpm_wave.do
Test Vectors fpmvectors LIST FILE error corrected
Path to library assign /rcc4/homes/degroat/ee762_assign
ASSIGNMENT SUMMARY TABLE
| STEP | Aspect of Language Introduced |
| Project Step 1 | The Generic Unit - DATAFLOW VHDL |
| Project Step 2 | ALU Slice - 1st Structural Architecture |
| Project Step 3 | 8 Bit ALU - Structural Hierachy |
| Project Step 4 | 1st Behavioral Architecture for 8 Bit ALU |
| Project Step 5 | 2nd Behavioral Architecture - Procedures/Functions |
| Project Step 6 | 3rd Behavioral Architecture - Packages/abstraction |
| Project Step 7 | Register set - modeling of busses & multi-value logic |
| Project Step 8 | Multiple drivers on a bus. Modeling of a more complex architecture having an ALU and registers. Introduced the need for type conversion. |
| Project Step 9 | Sequential machine design with VHDL (A synthesis coding style for sequential design is introduced) |
| Project Step 10 | Floating Point Adder - use of libraries, use of packages without having access to the code |