ECE 764 - Functional Verification of Hardware Designs

Spring 2012

Prof DeGroat's home page:: BACK

Course Syllabus:  ECE764/Syllabus_SP12.doc

LECTURES   (updates only to L1, L2 and Proj A desc)

WK 1

Lecture 1: Course Intro:  ECE764/Lectures/01 Lect 1-Course Overview.ppt

Lecture 2:  Floating Point Addition Project

Floating Point Lecture 1: ECE764/Lectures/Lect 2a -IEEE Floating Point Units.ppt

Floating Point Lecture 2: ECE764/Lectures/Lect 2b -IEEE Floating Point Adder Arch.ppt

Lecture 3: Verification Plans - Lect7_Verification_Plan.ppt   (Ill so moved to Monday)

WK 2

Verification Plans

Lecture 5: Constructing tests:   05 Lect6_Writing Tests.ppt

           VHDL Text IO including file write example: ECE764/Supplement Mtl/testread.vhdl 

Good Friday

WK 3

M3 Lecture 6: The Importance of Verification: ECE764/Lectures/06 Lect2-ImportanceOfVerification.ppt

W3 Lecture 4:  Directed Random Test: ECE764/Lectures/Lect 3 - Directed Radom Test.ppt

F3  Lecture 7: Checking the output: ECE764/Lectures/07 Lect11_CheckingTheOutput.ppt

      ECE764/Lectures/Fault Package Project outline.pptx 

WK 4

Lecture 10: Stimulus & Response: ECE764/Lectures/10 Lect10_Stimulus&Response.ppt

Lecture 11: Architecting Testbenches: ECE764/Lectures/11 Lect16_ArchitectingTestbenches.ppt

WK 5

W   Discussion on Fault simulator project

F    Discussion on Fault models.                         Test model is posted below in project section

WK 6

M  Lecture 11 - Architecting Testbenches

W   Lecture 15 Lect 14-Fault simulation Package.ppt

WK 7

M  The 762 Testbenches  19 Lect12_762Testbenches.ppt


WK 8


WK 9


WK 10



A. Floating Point Adder  (2012)

DUE: Test Plan - April 2 (or April 4) //// Report - April 13

Problem statement:  ECE764/Project 1 FPA/FPA.doc

Sample Test Vector File:  ECE764/Project 1 FPA/fpmvectors

Behavioral Reference Model:  

ECE764/Project 1 FPA/fpa.vhdl

ECE764/Project 1 FPA/fpa_support.vhdl

ECE764/Project 1 FPA/test_vect.vhdl              (note that these are examples)

  Dataflow Model to be verified:

ECE764/Project 1 FPA/fpa_df_v3.vhdl


B. (2012) - Implementation of a Package for fault testing

     Reference Week 3 Friday for project description

    Reference papers:   Fault Simulation Papers Bibliographic Entry.docx

       A mixed language fault sim.pdf      

       Behavioral Fault Simulation and ATPG.pdf

       Behavioral Fault Simulation in VHDL.pdf 

       Fault Simulation Basics.pdf 

       Joint and Marginal Prob Anaql of Markov.pdf 

    DUE DATES:   Verification Plan - (that covers development of the fault simulation logic system) - Friday April 28th

      VHDL model for testing of developed package

     Project B Fault Sim/mult_lin.vhdl     mult_support.vhdl     mult_tb.vhdl

        adder16.vhdl      adder8.vhdl

    A start ot the fsim_logic pagkage

     fsim_logic_1.vhdl    testfsim.vhdl

Project B Report due Monday May 21st.


PROJECT C:   Verification of Fault Tolerant Adder with package for fault testing of architecture.

     Test Plan : due Wednesday May 23

     Final Report : due Friday June 1

Architectures to be verified:

    Single Error Detecting (SED) Adder   - built stucturally

     files: full adder    Project C - FT adder/full_adder.vhdl

         fault tolerant slice    FT adder/sed_adder_slice.vhdl 

         4bit ft adder      sed_adder4.vhdl 

         8bit ft adder      sed_adder8.vhdl 

         type bit test bench   ft_adder_tb.vhdl 

           test bench package ft_adder_tb_support.vhdl 

The assignment - change the type to the fsim_logic type across the testbench and architectures and fault simulate to determine that the error signal is asserted when and error is injected.  NOTE:  in some cases the injected error may not result in an error.

    Single Error Correcting Adder - also built structurally 

  Single error correcting slice - sec_adder_slice.vhdl 

  8bit ft single error correcting adder - sec_adder8.vhdl 

The assignment on the sec adder is to insure that it can handle all single errors and still produce the correct result.  This means checking the adder output to the expected result.  With the int2bin and bin2int routines in the support package this is easy to incorporate into the testbench to do the self checking.  You also want to adjust the error injection threshold to find out when multiple errors are injected and not even detected or when the error is indicated as corrected but not corrected, i.e., when the adder does not live up to the error correcting billing.










old  prior B. we worked on a Floating Point Multiplier

Problem Statement:ECE764/Project 2 FPM/FPM assgn.doc

Behavioral code;  ECE764/Project 2 FPM/fpm.vhdl 

                          ECE764/Project 2 FPM/fpm_support_compl.vhdl

Dataflow code that need verification:ECE764/Project 2 FPM/FPM df Model.vhdl

                         vectors file: ECE764/Project 2 FPM/fpmvectors 

NOTES:  the model that is now posted handles all but Denormalized numbers.  Also, it may not correctly handle overflow to infinity.  It does seen to handle underflow.

The vectors file results need to be confirmed.  The vectors at then end of the file do not have the correct expected result.

Version 2 of Dataflow code: ECE764/Project 2 FPM/V2 FPM df Model.vhdl

NOTE on Version 2 - Handles all but Denormalized numbers.   Should correctly handle overflow to infinity.  This was handled by modifying the internal representation for theexponent summation to 10 bits the allow distinction between overflow conditions and   2's complement negative number representation.

Version 3 of Dataflow code: ECE764/Project 2 FPM/V3 FPM df Model.vhdl

Version 3 handles some Denormalized numbers.   The cases it does not handles are at the end of the transactions in the test vector file here:  ECE764/Project 2 FPM/V2 fpmvectors  The design group will be working on completion of the project so the race is on.  In fairness you are also being provided access to their testbench: ECE764/Project 2 FPM/testread.vhdl  The task: Look at the problem statement which has been ammended.

Version 4 of Dataflow code: ECE764/Project 2 FPM/V4 FPM df Model.vhdl

Version 4 is very close.   Seems to work correctly for all but a few cases.

C. Floating Point Execution sub-unit   ECE764/Project 3 FPx subunit/FPAFPM controller specification.doc



Material Covered

W 1 :  Lect 1

F 2 :  Project A     requirements

M 3: 

W 4: 

F 5: