ECE 764 - Functional Verificatio

The assignment - change the type to the fsim_logic type across the testbench and architectures and fault simulate to determine that the error signal is asserted when and error is injected. NOTE: in some cases the injected error may not result in an error.

The assignment on the sec adder is to insure that it can handle all single errors and still produce the correct result. This means checking the adder output to the expected result. With the int2bin and bin2int routines in the support package this is easy to incorporate into the testbench to do the self checking. You also want to adjust the error injection threshold to find out when multiple errors are injected and not even detected or when the error is indicated as corrected but not corrected, i.e., when the adder does not live up to the error correcting billing.

NOTES: the model that is now posted handles all but Denormalized numbers. Also, it may not correctly handle overflow to infinity. It does seen to handle underflow.

The vectors file results need to be confirmed. The vectors at then end of the file do not have the correct expected result.

NOTE on Version 2 - Handles all but Denormalized numbers. Should correctly handle overflow to infinity. This was handled by modifying the internal representation for theexponent summation to 10 bits the allow distinction between overflow conditions and 2's complement negative number representation.

Version 3 handles some Denormalized numbers. The cases it does not handles are at the end of the transactions in the test vector file here: ECE764/Project 2 FPM/V2 fpmvectors The design group will be working on completion of the project so the race is on. In fairness you are also being provided access to their testbench: ECE764/Project 2 FPM/testread.vhdl The task: Look at the problem statement which has been ammended.