EE762 Theory and Design of Computers, II
Hardware Description Languages
WINTER 2012 Assignments:
Syllabus: ee762/Syllabus-WI12.doc
Lectures (WI 2012)
W1: Lecture 1 - Course Introduction - ee762/LectWI09/L1 - Course Intro.ppt
F1: Lecture 2 - VHDL Introduction - ee762/LectWI09/Lect 2 - VHDL Introduction.ppt
HW 1 - Introduction to Modelsim : ee762/Assign_2012/HW 1 WI12.doc due Wed Jan 11, 2012
M2: Lecture 3 - Data Paths - Lect 3 - Data Paths 1.ppt
W2: Lecture 4 - Data Paths 2 - Lect 4 - Data Paths 2.ppt
Project Step 1 - Lect 3 - Project Step 1.ppt
F2: Lecture sync/Lecture 6 - Lect 6 - Language Overview I.ppt
W3: Continue with Language overview
Project Step 2 - Lect 5 - Project Step 2.ppt
F3: Language Overview - Lect 7 - Language Overview II.ppt
M4: Continue with Language Overview II
Project Step 3 - Lect 7 - Project Step 3.ppt
W4: Language Overview III - Lect 8 - Language Overview III.ppt
F4: Finish Language Overview - Attributes (package STANDARD)
Project Step 4 - Lect 9 - Project Step 4.ppt
M5: Attributes - Lect 10 - Attributes.ppt
Timing and concurrency I - Lect 12 - Timing & Concurrency I.ppt
W5: Project Step 5 - Lect 11 - Project Step 5.ppt
F5: Timing and Concurrency II - Lect 15 - Timing & Concurrency II.ppt
M6: Finish Timing and Concurrency II, Start Timing and Concurrency III - Lect 16 - Timing & Concurrency III.pdf
Project Step 6 = Lect 15 - Project Step 6.ppt
W6: Exam Review Midterm Exam Review.ppt
F6: Midterm Exam
M7: Finish Timing and Concurrency III - Resolution Lect 17 - Resolved Signals.ppt
W7: Resolution - Project Step 7 : Lect 18 - Project Step 7.pdf
F7: Finish Resolution
M8: Project Step 8 - Lect 20 - Project Step 8.ppt - State Machines - Lect 22 -State Machine Design.ppt
W8: Floating Point - Lect 24 -IEEE Floating Point Units.ppt
F8: Project Step 9 - Lect 23 - Project Step 9.ppt - Lect 23 - Project Step Extra Credit.pdf
Floating point units - Lect 24 -IEEE Floating Point Units.ppt Lect 25 - Project Step 10.ppt
M9: WORK ON ASSIGNMENTS
W9: WORK ON ASSIGNMENTS
F9: WORK ON ASSIGNMENTS
M10: floating point - Lect 25 -IEEE Floating Point Adder Arch.ppt
W10:
F10: std_1164.vhd
ASSIGNMENTS WI 2012:
| Assignment | Link | Due | Comments |
| HW1 | HW 1 WI12.doc | Wednesday Jan 11 | Intro to MODELSIM |
| PS1 |
pr_step1.vhdl PS1.doc |
Wednesday Jan 18 | The generic unit |
| PS2 |
pr_step2.vhdl PS2.doc |
Monday Jan 23 | A single ALU slice |
| PS3 |
pr_step3.vhdl
PS3.doc ps3_list.do ps3_wave.do |
Friday Jan 27 | 8 bit ALU and the generate statement |
| PS4 |
pr_step4.vhdl
PS4.doc p4_list.do p4_wave.do |
Wednesday Feb 1 | Using a process |
| PS5 |
pr_step5.vhdl
PS5.doc p5_list.do p5_wave.do |
Monday Feb 6 | Procedures declared in a process |
| PS6 |
pr_step6.vhdl
PS6.doc ps6_list.do ps6_wave.do |
Monday Feb 13 | Moving procedures to a package |
| PS7 |
pr_step7.vhdl
PS7.doc ps7_list.do ps7_wave.do |
Monday Feb 20 | Register set and busses |
| PS8 |
pr_step8.vhdl
PS8.doc ps8_list.do ps8_wave.do |
Friday Feb 25 | The datapath |
| PS9 | sar_tb.vhdl
PSsar.doc pssar_list.do pssar_wave.do |
Moday March 5 | State Machines |
| Extra Credit |
Extra Credit
step.doc pr_step_excr.vhdl excr_list.do excr_wave.do |
Monday March 5 | Adding Shifter to Data Path |
| PS10 |
PS10.doc
fpmtb.vhdl fpm_your_model.vhdl fpmvectors fpm_list.do fpm_wave.do |
Friday March 9 | Floating Point Multiplier |
Past offerings of course: ee762_web_page_2011.htm