ECE 561 - Digital Circuit Design

ECE 561 - Digital Circuit Design

Fall 2008

Prof DeGroat's Home Page : BACK

PROJECT 4 NOW POSTED!!!

Syllabus: ECE561/Syllabus561-FA08.doc

LECTURES

Lecture 1: ECE561/Lectures/ECE 561 - Lecture 1.ppt

Lecture 2: ECE561/Lectures/ECE 561 - Lecture 2.ppt

Lecture 3: ECE561/Lectures/ECE 561 - Lecture 3.ppt

Lecture 4: ECE561/Lectures/ECE 561 - Lecture 4 - State Machine Design.ppt

Lecture 5: ECE561/Lectures/ECE 561 - Lecture 5.ppt - State Machine Design Examples

Lecture 6: State Machine Realizations:ECE561/Lectures/ECE 561 - Lecture 6.ppt

Lecture 7: Using CAD Tools to Implement Digital Circuits:ECE561/Lectures/ECE 561 - Lecture 7.ppt

Lecture 8: Some VHDL Details: ECE561/Lectures/ECE 561 - Lecture 8.ppt

Lecture 9:

Lecture 10: Clock Skew and Clock Gating : ECE561/Lectures/ECE 561 - Lecture 10.ppt

Lecture 11: Configurable Programmable Logic Devices: ECE561/Lectures/ECE562 - Lect 11.ppt

Lecture 12: Memory ECE561/Lectures/ECE 561 - Lecture 12.ppt

Lecture 13: Memory 2: ECE561/Lectures/ECE 561 - Lecture 13.ppt

Lecture 14: ECE561/Lectures/ECE 561 - Lecture 14 - System Controller.ppt

Lecture 15: ECE561/Lectures/ECE 561 - Lecture 15 - Adders.ppt

Lecture 16: Using XILINX - ECE561/Lectures/ECE 561 - Lecture 16 - Heirarchy in Xilinx.ppt

Lecture 17: Sequential machine ex -ECE561/Lectures/ECE 561 - 762Lect 23 - Project Step 9.ppt

and the synthesized results: ECE561/Lectures/The SAR Synthesized Circuit.doc

WORKING!! - The following files for XILINX of the timer that not only simulate but also synthesize in XILINX so that you can push down through the schematics are here.

ECE561/XILINX_ex_working/cntrl.vhdl ECE561/XILINX_ex_working/dig.vhdl

Note that these use type BIT. They could also be done with type STD_LOGIC

A second example that will simulate with ModelSim - 3 file - the digits, the controller and a testbench

ECE561/XILINX_ex_complete/cntrl.vhdl ECE561/XILINX_ex_complete/dig.vhdl

ECE561/XILINX_ex_complete/cntr_tb.vhdl

Note that the digits file has is slightly different than its base version to reduce warning in XILINX. That version is here: ECE561/XILINX_ex_complete/dig.vhdl.old

ASSIGNMETNTS:

Assignment 1: Due WED Oct 1 - Probs 6.6, 6.44 parts a,b and e, 7.12

Assignment 2: (On last Slide of Lect 4) - Due Wed Oct 8

Assignment 3: (on last slide of Lect 5) - Due Fri Oct 10

Assignment 4: Do a VHDL specification of the fsm of Assignment 3: ECE561/Homework/Homework 4.doc

Assignment 5: Due Fri Oct 31: ECE561/Homework/Homework 5.doc

Assignment 6: www assignments in Lecture 12 - Due Monday Nov 3

Assignment 7: Prob 9.1 parts for Figures 6-37 and 6-73 - Due Wed Nov 5.

XILINX ASSIGNMETNTS:

NEW!!!! Project 4-Due Nov 24 - ECE561/XILINX_Proj/Using Xilinx to use VHDL as design entry.pdf

Guide to using VHDL in XILINX - ECE561/XILINX_Assignments/Instructions Using VHDL as the design entry in XILINX.doc

Proj1 - Due Nov 3 : description ECE561/XILINX_Proj/AU08_561proj1.pdf ISE files ECE561/XILINX_Proj/561proj1.zip