ECE 5462 HDL Design and Verification
Fall 2016 - MWF 5:20-6:15 Baker 144
Au 2016 Final Exam Period : Monday 12/12/16 4:00-5:45pm in classroom (for report presentations)
Course Syllabus : ECE5462/Syllabus/Syllabus-Au16 5462.doc
Material Covered :
HDL Lectures (below) -- Assignments and Proj Assgn (Assignments) -- Verification Lectures ( ) -- Verification Assgn ( )
HDL Lectures :
1W - 1 Course Intro and background : ECE5462/Lectures/L1 - Course Intro.ppt
1F - 2. Overview of VHDL capabilities : ECE5462/Lectures/Lect 2 - VHDL Introduction.ppt Homework 1 (due date below - use HWPS link above)
2M - Data Paths 1 - ECE5462/Lectures/Lect 3 - Data Paths 1.ppt
2W - Data Paths 2 - ECE5462/Lectures/Lect 4 - Data Paths 2.ppt PS01 - Project Step 1.ppt
2F - Language Overview I - ECE5462/Lectures/Lect 6 - Language Overview I.ppt
3W - Language Overview II - ECE5462/Lectures/Lect 7 - Language Overview II.ppt Lect PS02 - Project Step 2.ppt
3F - Language Overview III - ECE5462/Lectures/Lect 8 - Language Overview III.ppt
4M - Attributes of the Language - Lect 10 - Attributes.ppt Lect PS03 - Project Step 3.ppt
4W - Timing and Concurrency I - Lect 12 - Timing & Concurrency I.ppt
Solution to PS1 and PS2 : (only temporarily here) PS1 and 2 soln.ppt
4F - Timing and Concurrency II - Lect 15 - Timing & Concurrency II.ppt Lect PS04 - Project Step 4.ppt
5M - Finish T&C II - Timing and Concurrency III - Lect 16 - Timing & Concurrency III.ppt
5W - NO CLASS - student time to attend career fair
5F - Resolution - Lect 17 - Resolved Signals.ppt Lect PS05 - Project Step 5.ppt
6M - Finish Resolution -
6W - Project Step 6 - entire class period : Lect PS06 - Project Step 6.ppt
6F - Last Resolution execution example - Start State Machine - Lect 22 -State Machine Design.ppt
7M - State Machine Design // Project Step 7 - Register set Lect PS07 - Project Step 7.ppt
7W - State Machine Design
7F - PS8 - The datapath Lect PS08 - Project Step 8.ppt
8M - Floating point standard
8W - At NSF
9M - PS9 - A to D controller - Lect PS09 - Project Step 9.ppt
9W - Floating Point - Lect 24 -IEEE Floating Point Units.ppt
9F - Floating point execution Unit - Lect 26 -IEEE Floating Point Adder Arch.ppt /Lect 25 - Project Step 10.ppt
10M - on ABET Visit - no class
10W - Verification intro - intial groups Lect 28 Verif 1 - Verification Overview.ppt
10F - Verif proj 1 and verification plan. - Lect 29c-IEEE Floating Point Adder verification.ppt Lect 30_Verification_Plan.ppt
HW1 - a first run of Model Sim Homework/HW 1.doc Due : Wed October 31st, 2016
PS1 - a 4-to-1 Mux - Project/PS1.doc pr_step1.vhdl Due: Wed September 7
PS2 - Single ALU slice - Project/PS2.doc pr_step2.vhdl Due: Mon September 12th
PS3 - 8 Bit Alu (3 methods for structural) - Project Step 3.ppt Project/PS3.doc pr_step3.vhdl Due: Fri 9/16
PS4 - 1st behavioral - Project Step 4.ppt Project/PS4.doc pr_step4.vhdl p4_wave.do Due: Fri Sept 23
PS5 - 2nd behavioral - procedures - PS05 - Project Step 5.ppt Project/PS5.doc
pr_step5.vhdl p5_wave.do Due: Wed Sept 28
PS6 - 3rd behavior - symbolic operation - Lect PS06 - Project Step 6.ppt Project/PS6.doc
pr_step6.vhdl Project/ps6_wave.do Due: Mon Oct 3rd
PS7 - Dual Ported Register Set : Lect PS07 - Project Step 7.ppt Project/PS7.doc
Project/pr_step7.vhdl Project/ps7_wave.do Due : Oct 10th
PS8 - The data path - Lect PS08 - Project Step 8.ppt PS8.doc pr_step7.vhdl ps7_wave.do Due: Oct 20
PS 9 - The A-to-D controller - Lect PS09 - Project Step 9.ppt PSsar.doc sar_tb.vhdl sar_wave.do Due: Oct 26
PS 10 - Floating Pt Unit - PS10.doc fpmtb.vhdl fpmvectors test_vect.vhdl FPM_wave.do Due : Nov 2
Verif Proj 1 - Floating point adder - fpa.vhdl fpa_df_v3.vhdl fpa_support.vhdl fpadftb.vhdl fpatb.vhdl fpavectors
Proj Assgn A - FPA Verification.doc test_vect.vhdl
Verification Plan for proj 1 : Due 11/14
Verification Report for proj 1 : Due 11/21
Verif Proj 2 - A small processor design - MicroBaby spec v2.docx
files: mb_2.vhdl mbctl.vhdl mbdp.vhdl bstrpld.vhdl busdr8.vhdl clkdrv.vhdl load_mem.vhdl
mbaccum.vhdl mbalu.vhdl mbctl.vhdl mbspt.vhdl mem264.vhdl mux8_2to1.vhdl pcunit.vhdl
VERIFICATION PLAN DUE : Tues Dec 6
VERIFICATION REPORT DUE : Saturday Dec 10