ECE 5462
HDL Design and Verification - Au18
AU 2018 offering - Final Exam Period is Scheduled for Thursday December 13
(will be used for verification presentations if needed)
Course Syllabus: ECE5462/Syllabus/Syllabus-Au18 5462.doc
Material covered ( ) -- to come
HDL Lectures (Assignments HWPS ) Project Step slides (PSlds) (Verification Assignments (V Project Step 2: Project Step 2.ppt Assign)
W1. Course Intro and background : ECE5462/Lectures/L1 - Course Intro.ppt
2. Overview of VHDL capabilities : ECE5462/Lectures/Lect 2 - VHDL Introduction.ppt Homework 1 (due date below - use HWPS link above)
M3. Datapaths I : ECE5462/Lectures/Lect 3 - Data Paths 1.ppt
4. Datapaths II : Lect 4 - Data Paths 2.ppt Lect on PS1
5. Language Overview I : ECE5462/Lectures/Lect 6 - Language Overview I.ppt
M - LABOR DAY
W6. (Sept 5) Lect on PS2 Lect PS02 - Project Step 2.ppt Finish Lang Ov I, start Ov II
7. Language Overview II : Lect 7 - Language Overview II.ppt,
Language Overview III : Lect 8 - Language Overview III.ppt
M8. Attributes : Lect 10 - Attributes.ppt Project Step 3: Lect PS3 - Project Step 3.ppt
9. Timing and Concurrency I : Lect 12 - Timing & Concurrency I.ppt Soln to PS1 and PS2
10. Project Step 4: Lect PS04 - Project Step 4.ppt Demo on PS1 and PS2
M11. On Accreditation Visit - NO CLASS
12. Project Step 5 Lect PS05 - Project Step 5.ppt finish Timing and Concurrency I
13. Timing and Concurrency II Lect 15 - Timing & Concurrency II.ppt
M14. Timing and Concurrency III - Lect 16 - Timing & Concurrency III.ppt
Project Step 6 : Lect PS06 - Project Step 6.ppt
15. Class was a short question and answer due to number of students at career fair.
16. Resolution : Lect 17 - Resolved Signals.ppt
M17. Project Step 7 : Lect PS07 - Project Step 7.ppt Regosters
18. State Machine Design : Lect 22 -State Machine Design.ppt
19. PS7 Demo, State Machine Design
M20. PS8 Demo : Project Step 8 : Lect 20 - Project Step 8.ppt
21. Floating Point : Lect 24 -IEEE Floating Point Units.ppt Lect 26 -IEEE Floating Point Adder Arch.ppt
22. FRIDAY - FALL BREAK
M23. PS9 Lect PS09 - Project Step 9.ppt Extra Credit : Lect PXexcr - Project Step Extra Credit.ppt
24. PS10 - Floating Point Multiplier Project step 10 - Lect 25 - Project Step 10.ppt EXAM REVIEW
25. MIDTERM EXAM
M26. Verification Intro: Introduction to Verification : Lect 28 - Verification Overview.ppt
27.
28.
M28. (Nov) -
Friday Oct 30 - Boo!! There is class.
29. Verification Plan Lect 30_Verification_Plan.ppt
30. The first Verification Project : Lect 29c-IEEE Floating Point Adder verification.ppt
M31. Verification Project 1 - Exam Review Midterm Exam Review.ppt
W - VETRANS DAY _ NO CLASS
32. MIDTERM
M33. Verification Project 1
Re-emphasize what is in a plan - Floating point adder architecture : Lect 26 -IEEE Floating Point Adder Arch.ppt
Handling Denormalized Numbers Lect 29a-IEEE Floating Point Units - Handling denormalized.ppt
For reference : Lect 29a-IEEE Floating Point Units.ppt Lect 29b-IEEE FPA some verif slides at end.ppt
Verification Project 1 : Proj Assgn A - FPA Verification.doc Assignment files below
34. Writing Tests and Text I/O : ECE5462/Lectures/Lect 32 Writing Tests and TextIO.ppt
35. Midterm exam solution
M36. Verification Project 2 - MicroBaby architecture verification
THANKSGIVING
PRIOR Lectures
M29. Extra credit project Lect 23 - Project Step Extra Credit.ppt
22. -- Verilog overview Lect 27 - Verilog Intro.ppt
34. Directed Randon Test : Lect 31 - Directed Radom Test.ppt
HDL exam solution : Tansaction part - HDL Exam soln review.ppt List file: exam list Wave: exam trans prob wave.docx
36. The 762 testbenches : Lect 33_762Testbenches.ppt
M. 37 Verification Project 2 - Verifying Package fbit_logic - see verification project for links
The test plan for the FPA (revisited) - Lect 36 The FP adder test plan.ppt
38. Checking the output : Lect 34_CheckingTheOutput.ppt
M.40 Point to be covered in Verification Plan : Lect 35 Verification Project 2 Rubric.ppt
ps1 - Project Step 1 - Lect 3 - Project Step 1.ppt
ps2 - Project Step 2: Project Step 2.ppt
Homework and Project Steps Au 15 - VHDL
HW1 - a first run of Model Sim Homework/HW 1.doc NOT FOR TURN IN
PS1 - The generic unit - Project/PS1.doc Project step1.vhdl Due : Wed Sept 5 (Monday is a holiday)
PS2 - The 1-bit data path : Project/PS2.doc pr_step2.vhdl Due: Monday Sept 10th
PS3 - Structural ALU : PS3.doc pr_step3.vhdl ps3_list.do ps3_wave.do - Due Fri Sept 14th
PS4 - Procedural ALU : PS4.doc pr_step4.vhdl p4_list.do p4_wave.do - Due: Wed Sept 19th
PS5 - Procedural ALU 2 : PS5.doc pr_step5.vhdl p5_list.do p5_wave.do - Due: Wed Sep 26th
PS6 - Packages : PS6.doc pr_step6.vhdl ps6_list.do ps6_wave.do Due : Mon Oct 1st
PS7 - Registers : PS7.doc Project/pr_step7.vhdl ps7_list.do Project/ps7_wave.do Due : Fri Oct 5th
PS8 - Datapath - Registers and ALU : PS8.doc pr_step8.vhdl ps8_list.do ps8_wave.do Due : Mon Oct 15
PSexcr - Extra Credit - Shifter and Xoperation : PS Extra Credit step.doc pr_step_excr.vhdl use p8 do file Due:eos
PS9 - Sequential Machine - Psar : PSsar.doc sar_tb.vhdl sar_wave.do Due: Wed Oct 24
PS10 - Floating Point Multiplier PS10.doc test_vect.vhdl FPM/fpmvectors fpmtb.vhdl FPM_wave.do Due: Mon Oct 29
VERIFICATION ASSIGNMENTS (2018): (Updated 10/31/18)
VP1 : Floating Point Adder - Verification Plan Document : Due Mon Nov 12th
Final Verification Report : Due Wed Nov 21st
Grading Rubrics : ECE5462/Syllabus/AU18 Report rubrics.docx
Files: Reference Model - fpa.vhdl fpa_support.vhdl Test bench for ref mdl: fpatb.vhdl test_vect.vhdl
Testvector file : fpavectors The dataflow model to be verified : fpa_df_v3.vhdl
For Reference and applying vectors from fpmvectors use this file ECE5462/Verif Proj/fpatb.vhdl and the process in it.
VERIFICATION ORAL REPORTS - Final Week of Class - Dec 3 and Dec 5
Oral report on the Floating Point Adder Verification Effort
VP2 : Verification of a Microcontroller arch, MicroBaby
DUE DATES: VERIFICATION PROJECT 2 Plan Document : DUE Fri Nov 30th
VERIFICATION PROJECT 2 Report (all groups) : DUE Mon Dec 10th
The following files are a start on the project described in ECE5462/Verif Proj 2 Au14/MicroBaby spec.docx
ECE5462/Verif Proj 2 Au14/alu.vhdl ECE5462/Verif Proj 2 Au14/busdr8.vhdl ECE5462/Verif Proj 2 Au14/clkdrv.vhdl
ECE5462/Verif Proj 2 Au14/datamem ECE5462/Verif Proj 2 Au14/load_mem.vhdl ECE5462/Verif Proj 2 Au14/mb.vhdl
ECE5462/Verif Proj 2 Au14/mbaccum.vhdl ECE5462/Verif Proj 2 Au14/mbalu.vhdl ECE5462/Verif Proj 2 Au14/mbctl.vhdl
ECE5462/Verif Proj 2 Au14/mbdp.vhdl ECE5462/Verif Proj 2 Au14/mbspt.vhdl ECE5462/Verif Proj 2 Au14/mem264.vhdl
ECE5462/Verif Proj 2 Au14/mux8_2to1.vhdl ECE5462/Verif Proj 2 Au14/progmem
Udated microbaby specification document and files as of noon 12/3/2014
mb_2.vhdl mem264.vhdl mbctl.vhdl mbdp.vhdl bstrpld.vhdl clkdrv.vhdl datamem progmem
busdr8.vhdl mbaccum.vhdl mbalu.vhdl mbspt.vhdl mux8_2to1.vhdl pcunit.vhdl load_mem.vhdl
Updated files as of end of day 12/4/14 Only the updated files are below. The others are the same.
OF NOTE: direct addressing mode requires 3 cycles for execution. A tempAddrReg has been added to the controller.
1st cycle - MEM(PC) --> IR, PC+1-->PC
2nd cycle - MEM(PC)-->TempAddr PC+1-->PC (address is in instruction-fetched during 2nd cycle e_x)
3rd cycle - MEM(Temp Addr)--> destination or source-->MEM(TempAddr) This is cycle e2_x.
The Program Memory has 5 instructions encoded there.
LDA #$AA LDA #$55 LDA $10 LDA $11 STA $20
Initial simulation of these seem to work. The controller generation of control signals is not as clean as the design team
would like an it is in the process of being extended to other instructions and then it will be clean up for more steamlined coding.
A FURTHER UPDATE 12/9/14 2:00pm
The files below update the model to handle immediate mode ADD, SUB, AND, OR, XOR instruction and also add the flags register to the controller. The next step will be the CLRC (clear carry) and CLA instructions along the ADDC and SUBC immediate mode. Then the direct addressing mode will be implemented. Note that the interface to the controller changed which requied modification to mb_2.vhdl. The alu also has the fix of the error in calculation of the carry.
MicroBaby spec v2.docx mb_2.vhdl mbctl.vhdl mbalu.vhdl
Update - 12/11/14 12:00pm
After further work and fixing some issues, the design team has released some new files. They now have the clear carry flag, CCLR, and the set carry flag, CSET, instructions working. This required the addition of a latch on the B path input to the ALU of the datapath so that when the bus went to high impedance it did not change the flags to high impedance. All the immediate mode instructions are done. The list of the instrcutions working is : (page 13 of specification document) LDA # and $, STA $, ADD #, ADDC #, SUB #, SUBC #, AND #, OR #, XOR #, CLRC, CSET. Note that a couple of Op Codes have changed since CSET was added and one was already duplicated. The controller code is the golden reference on the Op Code for each instruction. The next step will be to get the direct addressing mode of these insturctions working. Regrettfully management has to have the design team work on a paper and project evaluations so this work will not be done until late in the weekend. The files with the current set working that have changes in them is included below. The specification document is a work in progess and needs some clean up. That will probably not happen until early next week.
MicroBaby spec v2.docx mb_2.vhdl.bak mbctl.vhdl mbalu.vhdl mbdp.vhdl datamem progmem
LAST YEARS
VERIFICATION ASSIGNMENTS (2013):
P2 : Verification of a SEC/DED add unit and packages fbit_logic and fsim_logic_package
ECE5462/Lectures/Lect 35_Verification Project 2.ppt
DUE DATES : Verification Plan : Due Tuesday November 26th
Verification Report : Due Wednesday December 4th
Verification Project presentation : Monday or Thursday Dec 2 or 5.
(There will be 3 groups presentating on Monday)
The SEC/DED adder unit
fulladd.vhdl
halfadd.vhdl
dualhalfadd.vhdl
(6 files)
sdadd8bit.vhdl
cnt8.vhdl
fill8.vhdl
fbit_logic package - fbit_logic.vhdl
(Ver 1.1 - type conversion to/from bit and bit_vector to/from fbit and fbit_vector added)
fsim_logic_package - fsim_logic.vhdl
Updated testbench code and do files: sar_tb_dl.vhdl sar_wave_13.do (either testbench should work)