ECE 5462

HDL Design and Verification  - Au15

AU 2015 offering   -  Final Exam Scheduled for Monday December 14 at 10:00am-11:45am

                                           (will be used for verification presentations)

Course Syllabus:   ECE5462/Syllabus/Syllabus-Au15 5462.doc    

Material covered (  ) -- to come

HDL Lectures  (Assignments  HWPS ) Project Step slides (PSlds)  (Verification Assignments (V Assign)     

W1. Course Intro and background :   ECE5462/Lectures/L1 - Course Intro.ppt

2. Overview of VHDL capabilities : ECE5462/Lectures/Lect 2 - VHDL Introduction.ppt    Homework 1  (due date below - use HWPS link above)

M3. Datapaths I :  ECE5462/Lectures/Lect 3 - Data Paths 1.ppt

4. Datapaths II :  Lect 4 - Data Paths 2.ppt     



M5. Language Overview I : ECE5462/Lectures/Lect 6 - Language Overview I.ppt 

6.   Continue Language Overview I          Project Step 2:  Project Step 2.ppt

7.    Finish Language Overview 1

M8.    Language Overview II : Lect 7 - Language Overview II.ppt   Project Step 3:   Lect PS3 - Project Step 3.ppt

9.    Finish Lang OV II _ Seq Stmts   Solutions and simultion - PS 1 and PS2

10.  Language Overview III : Lect 8 - Language Overview III.ppt  Project Step 4: Lect PS4 - Project Step 4.ppt

M 11.  Finish Lang Ov III :  Attributes  Lect 10 - Attributes.ppt 

12.   Project Step 5 : Lect PS5 - Project Step 5.ppt      (only a 45 minutes class due to career fair)

13.  Finish Timing and Concurrency I : Lect 12 - Timing & Concurrency I.ppt   

M 14. Finish Timing and Concurrency II  Lect 15 - Timing & Concurrency II.ppt  -  Project Step 6 : Lect 15 - Project Step 6.ppt 

15. Finish Timining and Conrrrency II :: Timing and Concurrency III -  Lect 16 - Timing & Concurrency III.ppt

16. Resolution : Lect 17 - Resolved Signals.ppt 

M17. Resolution to slide 33 - Project Step 7 : Lect 18 - Project Step 7.ppt

18.   AT NSF

19.    Finish Resolution -- Floating Point : Lect 24 -IEEE Floating Point Units.ppt

M20.   Floating Point wrap up --  Project Step 8 :  Lectures/Lect 20 - Project Step 8.ppt

21.       PS10 - Floating Point Multiplier   Project step 10 - Lect 25 - Project Step 10.ppt

22.    On Travel

M23.    On Travel -

24.   On travel - Review HDL State Machine Design :  Lect 22 -State Machine Design.ppt  -

25. (Oct 24)  Cleanup Floating Point  - State Machine Design

                        Project Step 9 : Lect 23 - Project Step 9.ppt

M26. Finish PS9 discussion  -   Introduction to Verification :   Lect 28 - Verification Overview.ppt   (to sl 6)

27.   Verification Intro

28.  PS7 and PS8 review, discussion, and simulation demo - Verification Plan    Lect 30_Verification_Plan.ppt

M29. Re-emphasize what is in a plan - Floating point adder architecture : Lect 26 -IEEE Floating Point Adder Arch.ppt

             Handling Denormalized Numbers Lect 29a-IEEE Floating Point Units - Handling denormalized.ppt

30.  The first Verification Project : Lect 29c-IEEE Floating Point Adder verification.ppt

        For reference : Lect 29a-IEEE Floating Point Units.ppt  Lect 29b-IEEE FPA some verif slides at end.ppt

        Verification Project 1 :    Proj Assgn A - FPA Verification.doc  Assignment files below


M32.  Exam Review of HDL modeling, architecture covered, HDL internal operation Midterm Exam Review.ppt

33.  Written in class Midterm Exam



  AU2013 offering - not yet updated


 Extra credit project Lect 23 - Project Step Extra Credit.ppt

 22.      -- Verilog overview   Lect 27 - Verilog Intro.ppt

34. Directed Randon Test : Lect 31 - Directed Radom Test.ppt

35. Writing Tests and Text I/O   : ECE5462/Lectures/Lect 32 Writing Tests and TextIO.ppt

       HDL exam solution : Tansaction part - HDL Exam soln review.ppt  List file: exam list  Wave: exam trans prob wave.docx

36. The 762 testbenches : Lect 33_762Testbenches.ppt

M. 37   Verification Project 2 - Verifying Package fbit_logic  - see verification project for links

        The test plan for the FPA (revisited) - Lect 36 The FP adder test plan.ppt

38.  Checking the output : Lect 34_CheckingTheOutput.ppt

39.  No class today

M.40  Point to be covered in Verification Plan : Lect 35 Verification Project 2 Rubric.ppt


Extra Credit -   May be posted over the holiday


  Project Step Slides

ps1 - Project Step 1 -  Project Step 1.ppt


Homework and Project Steps - VHDL   

HW1 - a first run of Model Sim    Homework/HW 1.doc      Due : Wed Sept 2nd, 2015

PS1 - The generic unit - Project/PS1.doc    Project/pr_step1.vhdl        Due : Wed Sept 9  (Monday was a holiday)






PS2 - The 1-bit data path : Project/PS2.doc   pr_step2.vhdl                 Due: Mon Sept 15th

PS3 - Structural ALU : PS3.doc     pr_step3.vhdl   - Due Fri Sept 19th

PS4 - Procedural ALU : PS4.doc  pr_step4.vhdl  - Due: Thurs Sept 25th

PS5- Procedural ALU 2 :  PS5.doc    pr_step5.vhdl - Due: Mon Sept 29rd

PS6 - Packages : PS6.doc    pr_step6.vhdl     Due : Fri Oct 3rd

PS7 - Registers :  PS7.doc   Project/pr_step7.vhdl   Project/  Due :  Fri Oct 10th

PS8 - Datapath : PS8.doc   pr_step8.vhdl     Due : Wed Oct 29th

PS10 - Floating Point Multiplier  PS10.doc  test_vect.vhdl  FPM/fpmvectors  fpmtb.vhdl Due: 10/29

    For Reference and applying vectors from fpmvectors use this file   ECE5462/Verif Proj/fpatb.vhdl  and the process in it.

   No mapping to shared library 

PS9 - Sequential Machine - Psar : PSsar.doc   sar_tb.vhdl     Due:  Wed Nov 5

              Updated testbench code and do files:   sar_tb_dl.vhdl  (either testbench should work)


VP1 : Floating Point Adder -   Verification Plan Document : Due Wed Nov 12th

                                                  Final Verification Report : Due Wed Nov 19th

       Files:  Reference Model - fpa.vhdl  fpa_support.vhdl   Test bench for ref mdl: fpatb.vhdl  test_vect.vhdl

                  Testvector file : fpavectors    The dataflow model to be verified :  fpa_df_v3.vhdl

 VP2 : Verification of a Microcontroller arch, MicroBaby

DUE DATES:   VERIFICATION PROJECT 2 Plan Document :  DUE Tuesday Dec 2

                          VERIFICATION PROJECT 2 Report  :   DUE   Sunday December 14th

                          VERIFICATION PROJECT 2 Final Presentation DRAFT : DUE Monday December 15th

                         VERIFICATION PROJECT 2 Final Presentation Slides : DUE Wednesday Dec 17th by NOON

The following files are a start on the project described in ECE5462/Verif Proj 2 Au14/MicroBaby spec.docx

ECE5462/Verif Proj 2 Au14/alu.vhdl  ECE5462/Verif Proj 2 Au14/busdr8.vhdl  ECE5462/Verif Proj 2 Au14/clkdrv.vhdl

ECE5462/Verif Proj 2 Au14/datamem   ECE5462/Verif Proj 2 Au14/load_mem.vhdl   ECE5462/Verif Proj 2 Au14/mb.vhdl

ECE5462/Verif Proj 2 Au14/mbaccum.vhdl   ECE5462/Verif Proj 2 Au14/mbalu.vhdl   ECE5462/Verif Proj 2 Au14/mbctl.vhdl

ECE5462/Verif Proj 2 Au14/mbdp.vhdl   ECE5462/Verif Proj 2 Au14/mbspt.vhdl   ECE5462/Verif Proj 2 Au14/mem264.vhdl

ECE5462/Verif Proj 2 Au14/mux8_2to1.vhdl   ECE5462/Verif Proj 2 Au14/progmem

   Udated microbaby specification document and files as of noon 12/3/2014

MicroBaby spec.docx

mb_2.vhdl   mem264.vhdl  mbctl.vhdl   mbdp.vhdl   bstrpld.vhdl  clkdrv.vhdl   datamem    progmem

busdr8.vhdl   mbaccum.vhdl   mbalu.vhdl   mbspt.vhdl   mux8_2to1.vhdl  pcunit.vhdl  load_mem.vhdl

  Updated files  as of end of day 12/4/14  Only the updated files are below.  The others are the same.

datamem           progmem        mbctl.vhdl

OF NOTE:  direct addressing mode requires 3 cycles for execution.   A tempAddrReg has been added to the controller.

1st cycle - MEM(PC) --> IR,    PC+1-->PC

2nd cycle - MEM(PC)-->TempAddr    PC+1-->PC   (address is in instruction-fetched during 2nd cycle e_x)

3rd cycle - MEM(Temp Addr)--> destination    or     source-->MEM(TempAddr)   This is cycle e2_x.

The Program Memory has 5 instructions encoded there.  

LDA  #$AA   LDA  #$55     LDA  $10      LDA  $11    STA  $20

Initial simulation of these seem to work.   The controller generation of control signals is not as clean as the design team

would like an it is in the process of being extended to other instructions and then it will be clean up for more steamlined coding.

A FURTHER UPDATE  12/9/14  2:00pm

The files below update the model to handle immediate mode ADD, SUB, AND, OR, XOR instruction and also add the flags register to the controller.   The next step will be the CLRC (clear carry) and CLA instructions along the ADDC and SUBC immediate mode.  Then the direct addressing mode will be implemented.   Note that the interface to the controller changed which requied modification to mb_2.vhdl.    The alu also has the fix of the error in calculation of the carry.

MicroBaby spec v2.docx   mb_2.vhdl     mbctl.vhdl    mbalu.vhdl

Update - 12/11/14     12:00pm

After further work and fixing some issues, the design team has released some new files.   They now have the clear carry flag, CCLR, and the set carry flag, CSET, instructions working.  This required the addition of a latch on the B path input to the ALU of the datapath so that when the bus went to high impedance it did not change the flags to high impedance.  All the immediate mode instructions are done.  The list of the instrcutions working is : (page 13 of specification document) LDA # and $, STA $, ADD #, ADDC #, SUB #, SUBC #, AND #, OR #, XOR #, CLRC, CSET.  Note that a couple of Op Codes have changed since CSET was added and one was already duplicated.  The controller code is the golden reference on the Op Code for each instruction.     The next step will be to get the direct addressing mode of these insturctions working.  Regrettfully management has to have the design team work on a paper and project evaluations so this work will not be done until late in the weekend.  The files with the current set working that have changes in them is included below.  The specification document is a work in progess and needs some clean up.  That will probably not happen until early next week.

MicroBaby spec v2.docx     mb_2.vhdl.bak      mbctl.vhdl     mbalu.vhdl     mbdp.vhdl     datamem    progmem



LAST YEARS                  


P2 : Verification of a SEC/DED add unit and packages fbit_logic and fsim_logic_package

ECE5462/Lectures/Lect 35_Verification Project 2.ppt

  DUE DATES :   Verification Plan : Due Tuesday November 26th

                              Verification Report : Due Wednesday December 4th

                              Verification Project presentation : Monday or Thursday Dec 2 or 5.

                                   (There will be 3 groups presentating on Monday)

       The SEC/DED adder unit fulladd.vhdl    halfadd.vhdl    dualhalfadd.vhdl
                    (6 files)                   sdadd8bit.vhdl    cnt8.vhdl     fill8.vhdl

       fbit_logic package - fbit_logic.vhdl  

                      (Ver 1.1 - type conversion to/from bit and bit_vector to/from fbit and fbit_vector added)

       fsim_logic_package  -  fsim_logic.vhdl