ECE 3561
Advanced Digital Design
Spring 2016 - 3:00-3:55pm - Scott 1005
Final Exam : FRIDAY April 29, 4:00-5:45 this room
SPRING 2015 Assign16ments and Quiz solutions
Syllabus : Syllabus3561 Adv Dig Dsgn - SP16.doc
Material Covered : Material Covered ECE5465 SP 16.docx
Midterm 2 : Midterm2
TAKE HOME Summary Exam : Exam 2 3561 - SP 2016.doc DUE : APRIL 29, 5pm
support files for Exam 2 : tb0101.vhdl tp4.vhdl Exam 2 3561 - SP 2016.pdf
LECTURES 2016
M1. Course Intro - ECE3561/Lectures/ECE 3561 - Lecture 01.ppt
2. Sequential Elements - Text Unit 11: Latches and Flip Flops - ECE3561/Lectures/ECE 3561 - Lecture 02.ppt
3. Memory Elements - Registers - ECE3561/Lectures/ECE 3561 - Lecture 03.ppt
W4. Traditional Sequential Machine Design - ECE 3561 - Lecture 5 Sequential Circuit Design Traditional.ppt
5. QUIZ 1 // State Graphs and State Tables - Creating State Graphs : ECE 3561 - Lecture 6 State Graphs and Tables.ppt
M6. State Graphs - Moore Machines - ECE 3561 - Lecture 7 State Graphs and Tables - Moore Machines.ppt
7. Examples of State Diagrams ECE 3561 - Lecture 7s - Multiple Output Example.ppt
8. NO CLASS - at IEEE Meetings in San Diego
M9. Feb 1 State Table Reduction - ECE 3561 - Lecture 8 State Reduction.ppt
10. Open session due to career fair
11. QUIZ 2 - State Assignment - Lecture 9 State Assignment.ppt
12M. AT NSF no class
13. Finish Lecture 9 - State Assignment - lots of class discussion
14. Quiz 3 on state table reduction (Implicaiton charts)
Other traditional State Machine topics - ECE 3561 - Lecture 10 State Machine Design Topics.ppt
15M Feb 15 -ONE hot from ECE 3561 - Lecture 10a additional State Machine examples.ppt
12. Finish State Machine Analysis - ECE 3561 - Lecture 11 State Machine Analysis.ppt
Board worked example problem 15.4
13. VHDL overview ECE 3561 - Lecture 12 VHDL Overview.ppt Quiz 4
M14. Feb 22 VHDL Language Elements ECE 3561 - Lecture 13 VHDL Language Elements.ppt
15. Finish VHDL Language Elements
16. Exam Review ECE 3561 - Lecture 11 Midterm Review.ppt
M17. Feb 29 MIDTERM 1
18. No class - AT DVCON
19. ECE 3561 - Lecture 14 VHDL Language Elements II.ppt
M20. VHDL specification of state machines : ECE 3561 - Lecture 15 VHDL Specification of State Machines.ppt
21. VHDL testbenches for state machines : ECE 3561 - Lecture 16 VHDL Testbenches for State Machines.ppt
M22. State Machines with binary encoding : ECE 3561 - Lecture 17 VHDL for State Machines with binary state encoding.ppt
23. SM assignments for the coming week. - QUARTIS Demo for assignments
24. TA coverage of HDL assignments
M25. TA - Coverage of use of Quartis and Report prep
26. TA work on assignments
27. Registers and Register Sets - Start on MicroBaby
M28. (Nov 2) Microbaby components
29. Resolved Signals ECE 3561 - Lecture 19 Resolved Signals.ppt
30. Ill - No class
M31. MB component assignments - ALU Design Today - ECE 3561 - Lecture 23 Arithmetic Logic Units.ppt
Wed - no class - Vetrans day
32. Adder architectures - ECE 3561 - Lecture 24 Alternative Adders.ppt
M33. The Microbaby Architecture
34.
35. CSA adders - add4.vhdl add4p0.vhdl add4p1.vhdl mux2t1x4.vhdl csa16.vhdl tcs16.vhdl
M36. The Microbaby projects 6 through 9 to complete the datapath
M37.
38.
39.
M40.
41.
VHDL Asssign 1 - VHDL Assign 1.doc DUE: 24 Feb
VHDL Assign 2 - VHDL Assign 2.doc DUE: 25 Mar
VHDL Assign 3 - VHDL Assign 3.doc DUE: 28 Mar
Microbaby ALU -Creation of MB ALU.docx DUE: 20 Apr
ECE 3561 - MB ALU creation.ppt mux2_1.vhdl mux2_1x8.vhdl
testbench for the alu talu.vhdl
COMPONENTS for use in the ALU and Datapath
Multiplexors mux2_1.vhdl mux2_1x8.vhdl mux4_1.vhdl mux4_1x8.vhdl
Register reg8.vhdl
Bus Driver busdr8.vhdl
8-bit All 0's detector can be written and a simple concurrent signal assignment
Microbaby Datapath - ECE 3561 -MicroBaby Datapath Creation.ppt DUE: 26 Apr by 5pm
ECE3561/Midterm2/Creation of MB Components.docx
Report mux2_1.docx Report mux2_1x8 brutus.1.docx
mux2_1.vhdl tb_mux2_1.vhdl mux2_1x8.vhdl tb_mux2_1x8.vhdl
PREVIOUS
4. Demonstration of Modelsim and Quartis - VHDL 2 assignment ECE 3561 - Lecture 4.ppt
M - Quartis Demo ECE 3561 - Quartis info.ppt
W Quartis Demo for timing and discussion of the MB Comp 6 assignment (Important in class discussion)
F State Machines for other counters/ Lecture 18 VHDL for other counters and controllers.ppt
Finish Lect 20 and Demo of work - ECE 3561 - Lecture 21 Register Set Testing.ppt
Register set testing - ECE 3561 - Lecture 22 Debugging the register set.ppt
Datapath integrating Register and ALU - ECE 3561 - Lecture 25 Datapath ALU.ppt
Sequential machine and cirucit analysis - Digital Systems Slides p2.pdf
Datapath and ALU - ECE 3561 - Lecture 26 Datapath ALU Structure and generation.ppt
M: Demo of quartis on full CPU unit
W: More demos of MB simulation in detail
F: More interactive work in class
M: Final Exam Review : ECE 3561 - Lecture 30 Final review.ppt
********************************************************************************************
AU2015 Assignments Asssignment Report Shell.docx
-- Read Unit 11 - Problem 11.1 - not to be turned in
-- Look at problems 11.1 / 11.4 / 11.8 / 11.10 / 11.11 Do Not Turn in - Answers are in Text
Problems and answers will be scanned and placed here.
********************************************************************************************