ECE 3561

ECE 3561

Advanced Digital Design

Autumn 2015 - 1:50-2:45pm - Journalism 300

Final Exam : Journalism 300 - Wednesday December 16 2:00-3:45pm

Au15 ECE 3561 - Lecture 30 Final review.ppt

SPRING 2015 Assignments and Quiz solutions

Syllabus : Syllabus3561 Adv Dig Dsgn - Au15.doc

Material Covered: coming

LECTURES

W1. Course Intro - ECE3561/Lectures/ECE 3561 - Lecture 01.ppt

2. Sequential Elements - Text Unit 11: Latches and Flip Flops - ECE3561/Lectures/ECE 3561 - Lecture 02.ppt

M3. Quiz 1 Memory Elements - Registers - ECE3561/Lectures/ECE 3561 - Lecture 03.ppt

SEPTEMBER 1

4. Demo of using Modelsim in class

5. Traditional Sequential Machine Design - ECE 3561 - Lecture 5 Sequential Circuit Design Traditional.ppt

W6. State Graphs and State Tables - Creating State Graphs : ECE 3561 - Lecture 6 State Graphs and Tables.ppt

7. State Graphs - Moore Machines - ECE 3561 - Lecture 7 State Graphs and Tables - Moore Machines.ppt

M8. Quiz 2 Examples of State Diagrams ECE 3561 - Lecture 7s - Multiple Output Example.ppt

9. State Table Reduction - ECE 3561 - Lecture 8 State Reduction.ppt (lect revised 9/14/15)

10. State Assignment - Lecture 9 State Assignment.ppt

M11. Quiz 3 Other traditional State Machine topics - ECE 3561 - Lecture 10 State Machine Design Topics.ppt

12. More on State Equivalence and one hot - ECE 3561 - Lecture 10a additional State Machine examples.ppt

13. State Machine Analysis - ECE 3561 - Lecture 11 State Machine Analysis.ppt

M14. Start VHDL overview ECE 3561 - Lecture 12 VHDL Overview.ppt

15. Quiz 4 VHDL overview

16. Exam Review ECE 3561 - Lecture 11 Midterm Review.ppt

M17. MIDTERM 1

18. Finish VHDL overview ECE 3561 - Lecture 13 VHDL Language Elements.ppt

19. ECE 3561 - Lecture 14 VHDL Language Elements II.ppt

M20. VHDL specification of state machines : ECE 3561 - Lecture 15 VHDL Specification of State Machines.ppt

21. VHDL testbenches for state machines : ECE 3561 - Lecture 16 VHDL Testbenches for State Machines.ppt

FALL BREAK

M22. Quiz 5 State Machines with binary encoding : ECE 3561 - Lecture 17 VHDL for State Machines with binary state encoding.ppt

23. SM assignments for the coming week. - QUARTIS Demo for assignments

24. TA coverage of HDL assignments

M25. TA - Coverage of use of Quartis and Report prep

26. TA work on assignments

27. Registers and Register Sets - Start on MicroBaby

M28. (Nov 2) Microbaby components

29. Resolved Signals ECE 3561 - Lecture 19 Resolved Signals.ppt

30. Ill - No class

M31. MB component assignments - ALU Design Today - ECE 3561 - Lecture 23 Arithmetic Logic Units.ppt

Wed - no class - Vetrans day

32. Adder architectures - ECE 3561 - Lecture 24 Alternative Adders.ppt

M33. The Microbaby Architecture

34.

35. CSA adders - add4.vhdl add4p0.vhdl add4p1.vhdl mux2t1x4.vhdl csa16.vhdl tcs16.vhdl

M36. The Microbaby projects 6 through 9 to complete the datapath

Wed and Fri - no class - Thanksgiving - TURKEY DAY!!!

M37.

38. (Dec 2)

39.

M40.

41.

PREVIOUS

4. Demonstration of Modelsim and Quartis - VHDL 2 assignment ECE 3561 - Lecture 4.ppt

M - Quartis Demo ECE 3561 - Quartis info.ppt

W Quartis Demo for timing and discussion of the MB Comp 6 assignment (Important in class discussion)

F State Machines for other counters/ Lecture 18 VHDL for other counters and controllers.ppt

Finish Lect 20 and Demo of work - ECE 3561 - Lecture 21 Register Set Testing.ppt

Datapath integrating Register and ALU - ECE 3561 - Lecture 25 Datapath ALU.ppt

Sequential machine and cirucit analysis - Digital Systems Slides p2.pdf

Datapath and ALU - ECE 3561 - Lecture 26 Datapath ALU Structure and generation.ppt

FINAL FULL WEEK

M: Demo of quartis on full CPU unit

W: More demos of MB simulation in detail

F: More interactive work in class

M: Final Exam Review : ECE 3561 - Lecture 30 Final review.ppt

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AU2015 Assignments Asssignment Report Shell.docx

-- Read Unit 11 - Problem 11.1 - not to be turned in

- VHDL 1 - (drop box VHDL 1) - Assignments/VHDL Assign 1.doc DUE: Friday Sept 4

- HW 1 (drop box HW 1) - ECE3561/HW/AU 15 HW 1.docx DUE: Monday Sept 14

- Text problem 15.1, 15.2, 15.3 - Not for turn in - Answers are in text

- VHDL 2 - (drop box VHDL 2) - Au 15 VHDL Assign 2.docx code file : vass2.vhdl DUE: Wed Oct 20

- VHDL 3 - (drop box VHDL 3) - AU 15 VHDL Assign 3.docx code file: vass3.vhdl DUE: Wed Oct 4

- VHDL 4 - (drop box VHDL 4) - AU 15 VHDL Assign 4.docx code file: vass4.vhdl DUE: Wed Oct 4

- VHDL 5 - (drop box VHDL 5) - AU 15 VHDL Assign 5.docx code file: vass4.vhdl DUE: Wed Oct 4

- VHDL 6 - (drop box VHDL 6) - AU 15 VHDL Assign 6.docx code file: vass4.vhdl DUE: Wed Oct 4

MICROBABY - sample report Mux 2-to-1 by 1 Report.docx

Mux2to1x8 - Au15 MB Comp 1.docx DUE: Mon 16 Nov

Mux4to1x1 - Au15 MB Comp 2.docx DUE: Wed 18 Nov

Mux4to1x8 - Au15 MB Comp 3.docx DUE: Wed 18 Nov

8-bit Register - Au15 MB Comp 4.docx DUE: Fri 20 Nov

all 0s detector - Au15 MB Comp 5.docx DUE: Fri 20 Nov

DUE TO MODELSIM LICESNE EXPIRATION DUE DATES EXTENDED

MORE INFO ON STRUCTURE ECE 3561 - Lecture 2x Microbaby Structure.ppt

Carry select adder - 8-bit - Au15 MB Comp 6.docx DUE: Mon 7 DEC DATES REVISED

MicroBaby ALU - structural - Au15 MB Comp 7.docx DUE: Wed Dec 9 Testbench talu.vhdl

Bus Driver - Au15 MB Comp 8.docx DUE: FRI Dec 11

MicroBaby Datapath - Au15 MB Comp 9.docx DUE: FRI Dec 11 testbench for dp tdp.vhdl

Integration with controller - Extra Cred - Au15 MB Comp 10.docx DUE: Mon Dec 14

bstrpld.vhdl clkdrv.vhdl load_mem.vhdl mb_2.vhdl mbctl.vhdl mbspt.vhdl mem264.vhdl pcunit.vhdl

datamem progmem Hook up to your datapath

Quiz Solutions

Au 15 Quiz 1 soln.docx Au 15 Quiz 2 soln.docx Au 15 Quiz 3 soln.docx Au 15 Quiz 4 soln.docx

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PREVIOUS

- VHDL 2 - Repeat class demo of Wednesday VHDL Assign 2.docx DUE: Feb 27

Files : fa.vhdl testfa.vhdl

- Computer assign 1 - coming

- HW2 - Lect 8 - Text chapter 14 - prob 14.26 - DUE : Feb 11

MB Comp 1,2,3,4 - DUE March 9

MB Comp 1.docx MB Comp 2.docx MB Comp 3.docx MB Comp 4.docx

MB Comp 5 - DUE March 13 8-bit 2-to-1 mux MB Comp 5.docx

MB Comp 6 - Due Apr 1 (Updated) Carry Select Adder MB Comp 6.docx test bench tfa.vhdl

MB Comp 7 - Logic Unit Due Apr 2 MB Comp 7.docx

MB Comp 8 - multi-function ALU Due: Fri Apr 10 (NEW DATE) MB Comp 8.docx

Testbench file for the ALU unit : talu.vhdl

MB Comp 9 - 8-bit register : DUE: Fri Apr 17 MB Comp 9.docx

MB Comp 10 - Bus Driver : DuE Fri Apr 17 MB Comp 10.docx

MB Comp 11 - The full CPU - Due Fri Apr 24 MB Comp 11 The CPU.docx The Testbench tbc.vhdl

The shell for the mbcpu unit : mbcpu.vhdl The .do file for waveform setup : mbcpuformat.do

Updated to here - 2/19/15

ECE 3561 - Lecture 5 Project 1.ppt

27. M Lect 20 - Registers and debugging Quartis ECE 3561 - Lecture 20 Register Set.ppt

28. W Lect 201 - Semester project datapath: ECE 3561 - Lecture 20a The 430 DP register set.ppt

29. F

ASSIGNMENTS SP 2014

1. See Lecture - Project 1 - CODE: cnt3.vhdl gen.vhdl DUE: Jan 22

2. Implement Excess 3 to BCD converter in an FPGA - HDL file : e3_bcd.vhdl Submit to dropbox HW2 DUE: Jan 31

3. HW 3 as described as the last slide of Lect 8 DUE to dropbox HW3 by Feb 3

4. Semester Project a 1 - Semester Project a 1.docx Due: Monday Feb 10 to dropbox HDL1

5. Semester Project a 2 - Semester Project a 2.docx Due: Wednesday Feb 19 to dropbox HDL2

6.Semester Project ms1 - Model Sim Overview.doc Logic Unit Simulation.doc logic_unit_tb.vhdl

Semester Project a 3.docx Due: Friday Feb 28 to dropbox HDL3

7. Semester Project a 4 - Semester Project a 4.docx Due: changed to Friday March 28

Some example code: mealy101.vhdl moore101.vhdl test101tb.vhdl

Some code that can help in creating testbench: CLKDIV.vhdl cnt8_Gray.vhdl

8. Semester Project a 5 - VHDL coding : Semester Project/Semester Project a 5.docx DUE: Mon Mar 7

reference code and overview: Reference Alu code and tb.docx

files: fa.vhdl fa16.vhdl lu.vhdl lu16.vhdl mux2_1.vhdl mux2_1x16.vhdl alu1.vhdl tbalu1.vhdl

9. Semester Project a 6 :- Semester Project a 6.docx

10. Semester Project a 7: Semester Project a 7.docx

This step is the ALU that get information from the busses and drives the results bus

NEW Semester Project a 7 additional info.docx teshbench for this step Semester Project/tbalu3.vhdl

Submission include HDL simulation and Quartis synthesis of the unit.

NEW Testbench for step a7 : tbalu3.vhdl

11. Semester Project a 8 : Semester Project a 8.docx Submit 6,7 and 8 to dropbox by end of semester.

This step is the register set. Semester Project a 8 document updated 4/16

TESTBENCH FOR A REGISTER LINE : tbreg.vhdl

TESTBENCH FOR THE REGISTER SET: tbregset.vhdl

NEW: testbench for the datapath testing just the registers : tbd1.vhdl

TESTBENCH for the datapath testing registers and alu : tbd2.vhdl support package dp430spt.vhdl

Description of the integration of the registers and alu : Semester Project a 9 - The datapath.docx

Autumn 2012 Offering

10. Lect 9 - State Assignment : ECE 3561 - Lecture 9 State Assignment.ppt

12. Quiz - Lect 10 - State equivalence and other topics: ECE 3561 - Lecture 10 State Machine Design Topics.ppt

14. Midterm Review ECE 3561 - Lecture 11 Midterm Review.ppt Quiz 1 soln.doc Quiz 2 soln.doc

answer to some HW problems ECE3561/Assignments/HW Solution.docx

Quiz 3 solution : Quiz 3 soln.doc

W 29