ECE 3561

Advanced Digital Design

SPRING 2015 - 8:00-8:55pm - Baker System 120

Final Exam : Baker Systems 120 - Thursday Apr 30 8:00-9:45am

 

SPRING 2015   Assignments

    Syllabus :  Syllabus3561 Adv Dig Dsgn - SP15.doc

    Material Covered:   Material Covered ECE3561 SP 15.docx

LECTURES

1. Course Intro - ECE3561/Lectures/ECE 3561 - Lecture 01.ppt

2. Sequential Elements - Text Unit 11: Latches and Flip Flops - ECE3561/Lectures/ECE 3561 - Lecture 02.ppt

3. Memory Elements - Registers - ECE3561/Lectures/ECE 3561 - Lecture 03.ppt

Monday Jan 19 - Martin Luther King Day

4.  Demonstration of Modelsim and Quartis - VHDL 2 assignment   ECE 3561 - Lecture 4.ppt  

Fri - No class

Monday Jan 26 - 6. Creating State Graphs :  ECE 3561 - Lecture 6 State Graphs and Tables.ppt

W - No class

7.  State Graphs - Moore Machines -  ECE 3561 - Lecture 7 State Graphs and Tables - Moore Machines.ppt

Feb 2, 2015

M - 9.  In class working of problem 14.5  ECE 3561 - Lecture 7 - worked on board.ppt

    - 10 -  State Table Reduction - ECE 3561 - Lecture 8 State Reduction.ppt

F  - 11 - QUIZ at end of class - State Assignment - Lecture 9 State Assignment.ppt

Feb 9, 2015

M - Other traditional State Machine topics - ECE 3561 - Lecture 10 State Machine Design Topics.ppt

W - Exam Review    ECE 3561 - Lecture 11 Midterm Review.ppt

F - Midterm 1 - Feb 13th

Feb 16, 2015

M - Return Midterms - ECE 3561 - Lecture 12 VHDL Overview.ppt

W - ECE 3561 - Lecture 13 VHDL Language Elements.ppt

F - Class Canceled due to -12 forcast (actual :~-8 at class time)

Feb 23, 2015

M - ECE 3561 - Lecture 14 VHDL Language Elements II.ppt  Quartis Demo ECE 3561 - Quartis info.ppt

W - VHDL specification of state machines : ECE 3561 - Lecture 15 VHDL Specification of State Machines.ppt

F -  VHDL testbenches for state machines : ECE 3561 - Lecture 16 VHDL Testbenches for State Machines.ppt

Mar 2, 2015

M -  At DVCON - no class but new assignments to work on

W-  At DVCON - no class but new assignments to work on

F- State Machines with binary encoding :  ECE 3561 - Lecture 17 VHDL for State Machines with binary state encoding.ppt

Mar 9, 2015

M  State Machines with binary encoding

W Quartis Demo for timing and discussion of the MB Comp 6 assignment (Important in class discussion)

F   State Machines for other counters/ Lecture 18 VHDL for other counters and controllers.ppt

Mar16, 2015 - SPRING BREAK   - March 16-20

Mar 23

M RESOLVED SIGNALS  ECE 3561 - Lecture 19 Resolved Signals.ppt

 

 

SP2015 Assignments    Asssignment Report Shell.docx

-- Read Unit 11 - Problem 11.1  - not to be turned in

- VHDL 1 - (drop box) - Assignments/VHDL Assign 1.doc    DUE : Jan 21

- VHDL 2 - Repeat class demo of Wednesday VHDL Assign 2.docx DUE: Feb 27

                       Files :    fa.vhdl      testfa.vhdl

- Computer assign 1 - coming

- HW2 - Lect 8 - Text chapter 14 - prob 14.26 - DUE : Feb 11

MB Comp 1,2,3,4 - DUE  March 9

                        MB Comp 1.docx      MB Comp 2.docx     MB Comp 3.docx   MB Comp 4.docx

MB Comp 5 - DUE March 13     8-bit 2-to-1 mux              MB Comp 5.docx

MB Comp 6 - Due Apr 1 (Updated)    Carry Select Adder      MB Comp 6.docx  test bench  tfa.vhdl

MB Comp 7 - Logic Unit     Due Apr 2   MB Comp 7.docx

MV Comp 8 - multi-function ALU     Due: Mon Apr 7   MB Comp 8.docx   testbench file coming

 

 

Updated to here - 2/19/15

                                                      ECE 3561 - Lecture 5 Project 1.ppt

 

 

27. M  Lect 20 - Registers and debugging Quartis  ECE 3561 - Lecture 20 Register Set.ppt

28. W Lect 201 - Semester project datapath:    ECE 3561 - Lecture 20a The 430 DP register set.ppt

29. F

 

ASSIGNMENTS SP 2014

1. See Lecture - Project 1 - CODE: cnt3.vhdl    gen.vhdl                 DUE: Jan 22

2. Implement Excess 3 to BCD converter in an FPGA -  HDL file : e3_bcd.vhdl  Submit to dropbox HW2  DUE: Jan 31

3. HW 3 as described as the last slide of Lect 8      DUE to dropbox HW3 by Feb 3

4. Semester Project a 1 - Semester Project a 1.docx   Due: Monday Feb 10 to dropbox HDL1

5. Semester Project a 2 - Semester Project a 2.docx   Due:  Wednesday Feb 19 to dropbox HDL2

6.Semester Project ms1 - Model Sim Overview.doc   Logic Unit Simulation.doc  logic_unit_tb.vhdl 

                 Semester Project a 3.docx                           Due: Friday Feb 28 to dropbox HDL3

7. Semester Project a 4 - Semester Project a 4.docx   Due: changed to Friday March 28

      Some example code: mealy101.vhdl     moore101.vhdl  test101tb.vhdl

     Some code that can help in creating testbench:  CLKDIV.vhdl   cnt8_Gray.vhdl

8. Semester Project a 5 - VHDL coding : Semester Project/Semester Project a 5.docx  DUE: Mon Mar 7

reference code and overview:   Reference Alu code and tb.docx

files: fa.vhdl  fa16.vhdl  lu.vhdl  lu16.vhdl  mux2_1.vhdl  mux2_1x16.vhdl  alu1.vhdl  tbalu1.vhdl

9. Semester Project a 6 :- Semester Project a 6.docx

10. Semester Project a 7:  Semester Project a 7.docx   

    This step is the ALU that get information from the busses and drives the results bus 

   NEW  Semester Project a 7 additional info.docx  teshbench for this step Semester Project/tbalu3.vhdl

     Submission include HDL simulation and Quartis synthesis of the unit. 

   NEW Testbench for step a7  :     tbalu3.vhdl

11. Semester Project a 8 :  Semester Project a 8.docx       Submit 6,7 and 8 to dropbox by end of semester.

     This step is the register set.      Semester Project a 8 document updated 4/16

     TESTBENCH FOR A REGISTER LINE :    tbreg.vhdl 

     TESTBENCH FOR THE REGISTER SET:    tbregset.vhdl 

NEW: testbench for the datapath testing just the registers :     tbd1.vhdl

           TESTBENCH for the datapath testing registers and alu :      tbd2.vhdl    support package  dp430spt.vhdl

      Description of the integration of the registers and alu :     Semester Project a 9 - The datapath.docx 

 

 

 

 

Autumn 2012 Offering

10. Lect 9 - State Assignment : ECE 3561 - Lecture 9 State Assignment.ppt

12. Quiz -  Lect 10 - State equivalence and other topics: ECE 3561 - Lecture 10 State Machine Design Topics.ppt

14.  Midterm Review ECE 3561 - Lecture 11 Midterm Review.ppt   Quiz 1  soln.doc   Quiz 2 soln.doc

                       answer to some HW problems   ECE3561/Assignments/HW Solution.docx 

Quiz 3 solution : Quiz 3 soln.doc

W 29

F 30  Finish Lect 20 and Demo of work  - ECE 3561 - Lecture 21 Register Set Testing.ppt

M 31 Register set testing  -   ECE 3561 - Lecture 22 Debugging the register set.ppt

W 32  ALU Design Today - ECE 3561 - Lecture 23 Arithmetic Logic Units.ppt

W 34 Adder architectures - ECE 3561 - Lecture 24 Alternative Adders.ppt

F 35 Datapath integrating Register and ALU - ECE 3561 - Lecture 25 Datapath ALU.ppt

M 36 Sequential machine and cirucit analysis - Digital Systems Slides p2.pdf

M 37 Datapath and ALU - ECE 3561 - Lecture 26 Datapath ALU Structure and generation.ppt

Final Exam Review : ECE 3561 - Lecture 30 Final review.ppt

 

HOMEWORK for turnin

1. 

 

 

Prior Offering

3. HW2 Homework - Problem 16.3 page 539  use the D F/F as stated in the problem and also implement it with T F/Fs.     :  Due Monday Sept 10

4. HW3 Problem 14.5 page 456 : Due W Sept 12

5. HW4 - Problem 14.12 page 457 : Due Mon Sept 17

6. HW5- In the lecture slides of Lect 9 repeat the implementation shown on slides 10, 11, and 12 for the rightmost assignment map.  The slides show the implementation of the leftmost assignment map.  Compare the number of gates used in your work versus the gates on the slides (slide 12).  For both assignment maps work out the number of gates need for the Z output.                         DUE: Friday Sept 21st

7. HW6 - VHDL assign I :     : Due Wed Oct 10

8. HW7 - VHDL assign 2 : Simple state machine : VHDL Assign 2.docx   Due Wed Oct 17

      For reference: from lectures  HDL - tbird.vhdl  Mealy101 - mealy101.vhdl   Moore101 - moore101.vhdl

9. HW8 - Synthesize the Simple state machine in VHDL Assign 2 - Due Fri Oct 19

10. HW9 - Counter - VHDL Assign 3.docx  - Due Fri Oct 26

11. HW10 - 3-to-8 decoder - VHDL Assign 4.doc - Due Monday Oct 29

12.  HW11 - 8 register dual ported register set built off of the 4 register implementation

     The files: busdr8.vhdl  m4drv.vhdl  decoder2to4.vhdl  mux2to1x8.vhdl  reg8.vhdl   reg_set_4.vhdl

     The testbench : regsettest.vhdl     The writeup :   VHDL Assign 5.doc  DUE : Wednesday Nov 14

13. HW12 - The core ALU unit - ref Lect 25 - DUE : Wed Nov 21

14. HW 13 - Core ALU unit with input registers output bus driver - DUE : Wed Nov 28   ref Lect 25

15. HW14 - Integration with register set - synthesize and HDL simulation : DUE : Wed Dec 5  ref Lect 25

         The following may be useful in modifying the regsettest.vhdl to run the datapath.   This is a datapath

  testbench from the HDL course that if for a datapath.   Note that it will not work directly but should be very

useful in what and how to modify the regsettest.vhdl for the final simulation.  pr_step8.vhdl