ENTITY mult_lin IS PORT (a,b : IN bit_vector(7 downto 0); c : OUT bit_vector(15 downto 0)); END mult_lin; ARCHITECTURE one OF mult_lin IS SIGNAL pr0,pr1,pr2,pr3,pr4,pr5,pr6,pr7 : bit_vector(15 downto 0); SIGNAL ps11,ps12,ps13,ps14 : bit_vector(15 downto 0); SIGNAL c11,c12,c13,c14 : bit_vector(15 downto 0); SIGNAL ps21,ps22,ps31 : bit_vector(15 downto 0); SIGNAL c21,c22,c31 : bit_vector(15 downto 0); SIGNAL mplr,mpcnd : bit_vector(7 downto 0); CONSTANT zerovec : bit_vector(15 downto 0) := "0000000000000000"; COMPONENT adder16 PORT (a,b : IN bit_vector(15 downto 0); sum : OUT bit_vector(15 downto 0)); END COMPONENT; FOR all : adder16 USE ENTITY work.adder16(one); BEGIN mplr <= a; mpcnd <= b; --Generate partial Products pr0 <= "00000000" & mpcnd WHEN (mplr(0)='1') ELSE zerovec; pr1 <= "0000000" & mpcnd & '0' WHEN (mplr(1)='1') ELSE zerovec; pr2 <= "000000" & mpcnd & "00" WHEN (mplr(2)='1') ELSE zerovec; pr3 <= "00000" & mpcnd & "000" WHEN (mplr(3)='1') ELSE zerovec; pr4 <= "0000" & mpcnd & "0000" WHEN (mplr(4)='1') ELSE zerovec; pr5 <= "000" & mpcnd & "00000" WHEN (mplr(5)='1') ELSE zerovec; pr6 <= "00" & mpcnd & "000000" WHEN (mplr(6)='1') ELSE zerovec; pr7 <= "0" & mpcnd & "0000000" WHEN (mplr(7)='1') ELSE zerovec; --First tier of adding to get partial results a11 : adder16 PORT MAP (pr0,pr1,ps11); a12 : adder16 PORT MAP (pr2,pr3,ps12); a13 : adder16 PORT MAP (pr4,pr5,ps13); a14 : adder16 PORT MAP (pr6,pr7,ps14); --Second tier of adding a21 : adder16 PORT MAP (ps11,ps12,ps21); a22 : adder16 PORT MAP (ps13,ps14,ps22); --3rd and final tier of adding a31 : adder16 PORT MAP (ps21,ps22,ps31); -- now have output c <= ps31; END one;