ENTITY adder8 IS PORT ( a,b : IN bit_vector(7 downto 0); sum : OUT bit_vector(7 downto 0)); END adder8; ARCHITECTURE one OF adder8 IS SIGNAL ic : bit_vector(8 downto 0); BEGIN ic(0) <= '0'; sum <= a XOR b XOR ic(7 downto 0); ic(8 downto 1) <= (a AND b) OR (a AND ic(7 downto 0)) OR (b AND ic(7 downto 0)); END one;