LIBRARY IEEE; USE IEEE.std_logic_1164.all; USE WORK.mbspt.all; ENTITY mem264 IS PORT (rw,ce : IN std_logic; addr : IN std_logic_vector (7 downto 0); data : INOUT std_logic_vector (7 downto 0)); END mem264; ARCHITECTURE one OF mem264 IS BEGIN PROCESS (rw,ce,addr,data) TYPE memwd IS ARRAY (0 to 255) of std_logic_vector (7 downto 0); VARIABLE mem : memwd; VARIABLE iaddr : integer; BEGIN IF (ce = '1') THEN IF (rw = '1') THEN --rw high so a write iaddr := bin8_2_int(addr); mem(iaddr) := data; ELSE iaddr := bin8_2_int(addr); data <= mem(iaddr); END IF; ELSE data <= "ZZZZZZZZ"; END IF; END PROCESS; END one;