LIBRARY IEEE; USE IEEE.std_logic_1164.all; ENTITY mbalu IS PORT(A,B : IN std_logic_vector(7 downto 0); res : OUT std_logic_vector(7 downto 0); cin : IN std_logic; Fun : IN std_logic_vector(3 downto 0); Arlo : IN std_logic; AddSub : IN std_logic; Cout,N,Z : OUT std_logic); END mbalu; ARCHITECTURE one OF mbalu IS SIGNAL Lout : std_logic; BEGIN -- Logic Unit Lout <= (NOT A AND NOT B AND Fun(0)) OR (NOT A AND B AND Fun(1)) OR (A AND NOT B AND Fun(2)) OR (A AND B AND Fun(3)); -- Prep B input to Add/Sub END;