LIBRARY IEEE; USE IEEE.std_logic_1164.all; USE WORK.mbspt.all; ENTITY PCunit IS PORT (pc : OUT std_logic_vector(7 downto 0); fixval : IN std_logic_vector(7 downto 0); pcsel,ldnewpc : IN std_logic; rst : IN std_logic); END PCunit; ARCHITECTURE one OF pcunit IS SIGNAL incrout,pcint,muxout : std_logic_vector(7 downto 0); BEGIN -- The loadable Program Counter Register PROCESS(ldnewpc,muxout,rst) BEGIN IF rst='0' THEN pcint <= "00000000"; ELSIF ldnewpc='1' AND ldnewpc'event THEN pcint <= muxout; END IF; END PROCESS; --Icrement PCint value incrout <= bin8_inc(pcint); --internal mux of new PC value muxout <= incrout WHEN pcsel='1' ELSE fixval; --Drive pc output pc <= pcint; END one;