LIBRARY IEEE; USE IEEE.std_logic_1164.all; ENTITY mux8_2to1 IS PORT(minl,minr : IN std_logic_vector(7 downto 0); msel : IN std_logic; mout : OUT std_logic_vector(7 downto 0)); END mux8_2to1; ARCHITECTURE one OF mux8_2to1 IS BEGIN mout <= minl WHEN msel='1' ELSE minr; END one;