LIBRARY IEEE; USE IEEE.std_logic_1164.all; ENTITY mbctl IS PORT(stld : OUT std_logic; ldcmpl : IN std_logic; Dbus : IN std_logic_vector(7 downto 0); addr : OUT std_logic_vector(7 downto 0); rst : IN std_logic; clk,mclk : IN std_logic; rw,ice : OUT std_logic; dce : OUT std_logic; Aal,Bbu,Ldacc,Dracc,AddSub,Arlo : OUT std_logic; Csel : OUT std_logic_vector(1 downto 0); Funct : OUT std_logic_vector(3 downto 0)); END mbctl; ARCHITECTURE one OF mbctl IS TYPE state_type IS (reset,loading,f1,f2,f3,f4,f5,f6,f7,f8,e1,e2,e3,e4,e5,e6,e7,e8); SIGNAL state,next_state : state_type; --declare signals for internal units SIGNAL pc,ir : std_logic_vector(7 downto 0) := "00000000"; SIGNAL ldnewpc,pcsel : std_logic; --declare control signals for datapath SIGNAL dpcsvec : std_logic_vector(0 to 6); SIGNAL dpfunvec : std_logic_vector(3 downto 0); SIGNAL memcsvec : std_logic_vector(1 downto 0); --declare internal components COMPONENT PCunit IS PORT (pc : OUT std_logic_vector(7 downto 0); fixval : IN std_logic_vector(7 downto 0); pcsel,ldnewpc : IN std_logic; rst : IN std_logic); END COMPONENT; FOR all : pcunit USE ENTITY WORK.PCunit(one); BEGIN --FF process to latch next_state to state or set state when rst PROCESS (mclk) BEGIN IF (rst='0') THEN state <= reset; ELSIF (mclk'event) THEN state <= next_state; END IF; END PROCESS; PROCESS (state,ldcmpl) BEGIN --FF to latch next_state to state or set state when r CASE state IS WHEN reset => addr <= "ZZZZZZZZ"; stld <= '1'; rw <= 'Z'; ice <= 'Z'; dce <= 'Z'; next_state <= loading; ldnewpc <= '0'; pcsel <= '1'; Aal <= '0'; Bbu <= '0'; Ldacc <= '0'; Dracc <= '0'; AddSub <= '0'; Arlo <= '0'; Csel <= "00"; WHEN loading => IF ldcmpl='1' THEN next_state<=f1; stld <= '0' AFTER 5 ns; END IF; WHEN f1 => ldnewpc<='0'; next_state<=f2; WHEN f2 => rw<='0'; addr<=pc; next_state<=f3; WHEN f3 => ice<='1'; dce<='0'; next_state<=f4; WHEN f4 => ir<=Dbus; next_state<=f5; WHEN f5 => next_state<=f6; WHEN f6 => ldnewpc <= '0'; CASE ir IS WHEN "10000001" => --LDA Immediate dpcsvec <= "0110000"; dpfunvec <= "0000"; memcsvec <= "00"; WHEN OTHERS => null; END CASE; next_state<=f7; WHEN f7 => ice <= '0'; next_state<=f8; WHEN f8 => pcsel <= '1'; ldnewpc <= '1'; addr<="ZZZZZZZZ"; next_state<=e1; WHEN e1 => --first execute state next_state<=e2; ldnewpc <= '0'; WHEN e2 => --second execute state rw <= memcsvec(1); addr <= pc; next_state<=e3; WHEN e3 => IF memcsvec(0)='0' THEN ice<='1'; ELSE dce<='1'; END IF; next_state<=e4; WHEN e4 => next_state<=e5; WHEN e5 => next_state<=e6; WHEN e6 => next_state<=e7; WHEN e7 => IF dpcsvec(2)='1' THEN Ldacc <= '1'; END IF; next_state<=e8; WHEN e8 => ice <='0'; dce <= '0'; Ldacc <= '0'; IF memcsvec(0)='0' THEN ldnewpc<='1'; END IF; next_state<=f1; WHEN others => null; END CASE; END PROCESS; -- INSTANTIATE INTERNAL COMPONENTS pcu : pcunit PORT MAP (pc,"00000000",pcsel,ldnewpc,rst); END one;