--=========================================================================
-- Sequential Machine Problem
--
-- NAME:
--
--=========================================================================
-- PUT your Entity for the SAR here


--=========================================================================
-- PUT your Architecture for the SAR here


--=========================================================================
--*************************************************************************
-- support package for test bench
PACKAGE sar_pkg IS
  PROCEDURE d2a (digital_in : IN BIT_VECTOR (7 downto 0);
                 analog_out : OUT REAL);
END sar_pkg;

PACKAGE BODY sar_pkg IS

PROCEDURE d2a (digital_in : IN BIT_VECTOR (7 downto 0);
               analog_out : OUT REAL) IS
TYPE wt_tbl_type IS ARRAY (7 downto 0) OF REAL;
CONSTANT wt_tbl : wt_tbl_type := 
         (0.5,0.25,0.125,0.0625,0.03125,0.015625,0.0078125,0.00390625);
CONSTANT max_analog : REAL := 5.0;
VARIABLE analog_val : REAL;
BEGIN -- procedure d2a
analog_val := 0.0;
FOR I IN 7 DOWNTO 0 LOOP
  IF (digital_in(I) = '1')
    THEN  analog_val := analog_val + max_analog * wt_tbl(I);
  END IF;
END LOOP;
  analog_out := analog_val;
END d2a; --procedure

END sar_pkg;
--=========================================================================
--*************************************************************************
ENTITY stb IS END stb;

USE WORK.sar_pkg.ALL;
ARCHITECTURE test OF stb IS
-- Set up type and array of input test values
TYPE analog_in_tbl_type is array (1 to 15) of REAL;
CONSTANT analog_in_tbl : analog_in_tbl_type :=
  (0.0,0.5,1.0,1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,2.25,1.04,3.72,2.91);
-- Set up type and array for expected output values
TYPE dig_out_tbl_type is array (1 to 15) of BIT_VECTOR (7 downto 0);
CONSTANT dig_out_tbl : dig_out_tbl_type :=
    ("00000000","00011001","00110011","01001100","01100110",
     "01111111","10011001","10110011","11001100","11100110",
     "11111111","01110011","00110101","10111110","10010100");
-- output test number
SIGNAL vector_no : INTEGER := 0;
SIGNAL error,lsb_error : BIT := '0';
SIGNAL exp_val : BIT_VECTOR (7 downto 0);

-- Declare Signals for interfacing to the SAR digital section
SIGNAL sarclk : BIT := '0';
SIGNAL digital_val,sar_val : BIT_VECTOR (7 downto 0);
SIGNAL start,over_under,eoc : BIT; -- over='1', under='0'

-- Signals needed in analog section
SIGNAL analog_input,dac_out : REAL := 0.0;

-- **************** Declare and Config. Component here ******************

--***********************************************************************
BEGIN -- test architecture
-- *************************instantiate the component here **************


-- set up free running sarclk with a period of 100 ns.
sarclk <= NOT sarclk AFTER 50 ns;

-- Analog compnent modeling
PROCESS (analog_input,sar_val)
VARIABLE dac_out_var : REAL;
BEGIN -- Analog component model process
d2a (sar_val,dac_out_var);
dac_out <= (dac_out_var - 0.0001) after 19 ns, dac_out_var after 20 ns;
IF (dac_out_var >= analog_input) THEN over_under <= '1' after 40 ns;
                             ELSE over_under <= '0' after 40 ns;
END IF;
END PROCESS; -- Analog component model process

-- process to apply tests
applytest : PROCESS
BEGIN -- PROCESS applytest
FOR I IN analog_in_tbl'RANGE LOOP
  vector_no <= I;
  start <= '0';
  wait for 150 ns;
  analog_input <= (analog_input + 0.0001), (analog_in_tbl(I)+0.0001) AFTER 1 ns,
                     analog_in_tbl(I) AFTER 2 ns;
  exp_val <= dig_out_tbl(I);
  WAIT FOR 100 ns;
  start <= '1';
  WAIT UNTIL (eoc = '1');
  WAIT FOR 10 ns;
  -- now check results
  IF (digital_val(7 downto 1) /= dig_out_tbl(I)(7 downto 1))
    THEN error <= '1', '0' AFTER 1 ns;
  END IF;
  IF (digital_val(0) /= dig_out_tbl(I)(0))
    THEN lsb_error <= '1', '0' AFTER 1 ns;
  END IF;
  WAIT FOR 90 ns;
END LOOP;
WAIT FOR 100 ns;
WAIT;
END PROCESS applytest;

END test; --architecture