-------------------------------------------------------------------------------
-- Project Step 7 - Using busses
--
-- NAME:
--
-------------------------------------------------------------------------------
--  Enter the ENTITY for the register set here
-------------------------------------------------------------------------------



-------------------------------------------------------------------------------
--  Enter the Architecture for the register set here
-------------------------------------------------------------------------------




-------------------------------------------------------------------------------
--  Test Bench Entity for the Register set
-------------------------------------------------------------------------------
ENTITY  p7 IS
END p7;

LIBRARY  IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ARCHITECTURE test OF p7 IS

SIGNAL  ABUS,BBUS : std_logic_vector (15 downto 0);
SIGNAL  Aload,Bload,Adrive,Bdrive : std_logic;
SIGNAL  AregNo,BregNo : integer := 0;
CONSTANT  HighZ : std_logic_vector (15 downto 0) := "ZZZZZZZZZZZZZZZZ";
TYPE   vals_type IS array (0 to 3) of std_logic_vector (15 downto 0);
CONSTANT  Vals  : vals_type := ("0000000000000000","1111111111111111",
          "0110011001100110","1100000110000001");
SIGNAL Abus_err, Bbus_err : BIT;
TYPE LDItype IS (Load,Drive,Idle); 

-- ENTER THE COMPONENT DECLARATION AND CONFIGURATION HERE




-- Enter your name in the (  )
TYPE mname IS (yourname);
SIGNAL nm : mname := mname'VAL(0);

BEGIN -- the architecture
------------------------------------------------------------------------
-- ENTER YOUR COMPONENT INSTANTIATION FOR THE REGISTER SET HERE




------------------------------------------------------------------------
------------------------------------------------------------------------
applytest : PROCESS
------------------------------------------------------------------------
PROCEDURE applyNtest (A_ldi : LDItype; A_reg_no : Integer;
                      A_BUS_VAL : std_logic_vector (15 downto 0);
                      A_BUS_EXP : std_logic_vector (15 downto 0);
                      B_ldi : LDItype; B_reg_no : Integer;
                      B_BUS_VAL : std_logic_vector (15 downto 0);
                      B_BUS_EXP : std_logic_vector (15 downto 0)) IS
BEGIN
WAIT FOR 9 NS; --  9 ns into cycle
  IF (ABUS /= HighZ) THEN Abus_err <= '1','0' after 1 ns; END IF;
  IF (BBUS /= HighZ) THEN Bbus_err <= '1','0' after 1 ns; END IF;
WAIT FOR 1 NS; -- 10 ns into cycle
AregNo <= A_reg_no; BregNo <= B_reg_no;
CASE A_ldi IS
  WHEN Load  => Aload  <= '0'; ABUS <= A_BUS_VAL;
  WHEN Drive => Adrive <= '0'; 
  WHEN Idle  => null;
END CASE;
CASE B_ldi IS
  WHEN Load  => Bload  <= '0'; BBUS <= B_BUS_VAL;
  WHEN Drive => Bdrive <= '0'; 
  WHEN Idle  => null;
END CASE;
WAIT FOR 10 NS; -- 20 ns into cycle
  IF (ABUS /= A_BUS_EXP) THEN Abus_err <= '1','0' after 1 ns; END IF;
  IF (BBUS /= B_BUS_EXP) THEN Bbus_err <= '1','0' after 1 ns; END IF;
WAIT FOR 49 NS; -- 69 ns into cycle
  IF (ABUS /= A_BUS_EXP) THEN Abus_err <= '1','0' after 1 ns; END IF;
  IF (BBUS /= B_BUS_EXP) THEN Bbus_err <= '1','0' after 1 ns; END IF;
WAIT FOR  1 NS; -- 70 ns into cycle
IF (A_ldi = Load) THEN Aload <= '1'; END IF;
IF (B_ldi = Load) THEN Bload <= '1'; END IF;
WAIT FOR 10 NS; -- 80 ns into cycle
IF (A_ldi = Drive) THEN Adrive <= '1';
                   ELSE ABUS <= HighZ; END IF;
IF (B_ldi = Drive) THEN Bdrive <= '1';
                   ELSE BBUS <= HighZ; END IF;
WAIT FOR 11 NS; -- 91 ns into cycle
  IF (ABUS /= HighZ) THEN Abus_err <= '1','0' after 1 ns; END IF;
  IF (BBUS /= HighZ) THEN Bbus_err <= '1','0' after 1 ns; END IF;
WAIT FOR  9 NS; -- end of 100 ns cycle
END applyNtest;
------------------------------------------------------------------------

BEGIN -- the process
  ABUS <=  HighZ;  BBUS <= HighZ;
  AregNo <= 0;     BregNo <= 0;
  Aload  <= '1';   Bload  <= '1';
  Adrive <= '1';   Bdrive <= '1';
  -------------------------------------------------------------------
  -- TEST LOADING AND READING VALUES ONE AT A TIME
  -------------------------------------------------------------------
  FOR I in 0 to 15 Loop
  -- load values into register I using A bus and redrive it on A bus
    FOR J in 0 to 3 LOOP
      applyNtest(load,I,Vals(J),Vals(J),idle,I,HighZ,HighZ);
      applyNtest(drive,I,HighZ,Vals(J),idle,I,HighZ,HighZ);
    END LOOP;
  -- drive last value input into register I onto B bus
    applyNtest(idle,I,HighZ,HighZ,drive,I,HighZ,Vals(3));
  -- load values into register I using B bus and redrive it on B bus
    FOR J in 0 to 3 LOOP
      applyNtest(idle,I,HighZ,HighZ,load,I,Vals(J),Vals(J));
      applyNtest(idle,I,HighZ,HighZ,drive,I,HighZ,Vals(J));
    END LOOP;
  -- drive last value onto A Bus
    applyNtest(drive,I,HighZ,Vals(3),idle,I,HighZ,HighZ);
  END Loop;
  -------------------------------------------------------------------
  -- TEST LOADING ONE REGISTER FROM A BUS AND ANOTHER FROM B BUS
  -------------------------------------------------------------------
  For I in 0 to 7 Loop
    applyNtest(load,I,Vals(I MOD 4),Vals(I MOD 4),
               load,15-I,Vals((15-I) MOD 4),Vals((15-I) MOD 4));
    applyNtest(drive,15-I,HighZ,Vals((15-I) MOD 4),
               drive,I,HighZ,Vals(I MOD 4));
  END Loop;
  -------------------------------------------------------------------
  -- TEST LOADING ON ONE BUS AND DRIVING ON THE OTHER
  -------------------------------------------------------------------
  -- load a predetermined value in each register
  For I in 0 to 7 Loop
    applyNtest(load,I,Vals((I+1) MOD 4),Vals((I+1) MOD 4),
               drive,15-I,HighZ,Vals((15-I) MOD 4));
    applyNtest(drive,I,HighZ,Vals((I+1) MOD 4),
               load,15-I,Vals((15-I) MOD 4),Vals((15-I) MOD 4));
  END Loop;
  -------------------------------------------------------------------
  WAIT;
END PROCESS;

nm <= mname'VAL(0);

END test;