library ieee; use ieee.std_logic_1164.all; use STD.TEXTIO.all; entity fpmtb is end fpmtb; architecture my_test of fpmtb is signal A,B,C : std_logic_vector (31 downto 0); signal exp_res : std_logic_vector (31 downto 0); signal latch,drive : std_ulogic := '0'; signal aid_sig, bid_sig, resid_sig : string(1 to 6) := "======"; signal err_sig : bit; signal score : integer := 0; -- Place your component declaration and configuration here component fpm PORT (A,B : IN std_logic_vector (31 downto 0); latch, drive: IN std_ulogic; C : OUT std_logic_vector (31 downto 0)); end component; for all : fpm use ENTITY work.fpm(behavioral); --Enter your name in the ( ) TYPE mname IS (yourname); SIGNAL nm : mname := mname'VAL(0); BEGIN -- test architecture -- Instantiate your component here fpm0: fpm PORT MAP(A,B,latch,drive,C); gen_vec(aid_sig,bid_sig,resid_sig,A,B,exp_res,C,latch,drive,err_sig,score); nm<= mname'VAL(0); end my_test;