-------------------------------------------------------------------------------
--  EE762 - SP MS 1
--
--  NAME:
--
--=============================================================================
--  Generic Function Unit Entity
-------------------------------------------------------------------------------
ENTITY logic_unit IS
  PORT (A,B,C3,C2,C1,C0 : IN BIT;
        R  : OUT  BIT);
END logic_unit;

-------------------------------------------------------------------------------
--  Enter your architecture for the generic function unit here
-------------------------------------------------------------------------------

  







-------------------------------------------------------------------------------
--  The Test Bench Entity for testing of the generic function block
-------------------------------------------------------------------------------
ENTITY ms1 IS
END ms1;

-------------------------------------------------------------------------------
--  The Test Bench Architecture
-------------------------------------------------------------------------------
ARCHITECTURE test OF ms1 IS

  TYPE operations IS (opZERO,opNOR,opAbarB,opNOTA,
     opABbar,opNOTB,opXOR,opNAND,opAND,opXNOR,opB,
     opABARorB,opA,opAorBbar,opOR,opONE);
  TYPE oper_type  IS ARRAY (0 to 15) of operations;
  CONSTANT      oper_tbl     : oper_type := (opZERO,opNOR, 
       opAbarB,opNOTA,opABbar,opNOTB,opXOR,opNAND,opAND, 
       opXNOR,opB,opABARorB,opA,opAorBbar,opOR,opONE);
  SIGNAL        oper : operations;

  TYPE  gval_tbl_type IS ARRAY (0 to 15) of bit_vector (3 downto 0);
  CONSTANT gval_tbl : gval_tbl_type :=("0000","0001","0010", 
      "0011","0100","0101","0110","0111","1000","1001", 
      "1010","1011","1100","1101","1110","1111");
  SIGNAL        gval    : bit_vector (3 downto 0);

  SIGNAL        A,B,R            : bit;

  --  component declaration and configuration
  --  **** you must enter the architecture name ARCH_NAME
  --  in the FOR ALL statment below

  COMPONENT logic_unit
    PORT (A,B,C3,C2,C1,C0 : IN BIT;
          R  : OUT  BIT);
  END COMPONENT;
  FOR ALL : logic_unit USE ENTITY WORK.logic_unit(ARCH_NAME); 

BEGIN  --  test 

  g0 : logic_unit PORT MAP(A,B,gval(3),gval(2),gval(1),gval(0),R);

  applytests : PROCESS
  BEGIN  --  PROCESS applytests 
    outter: FOR i IN 0 TO 15 LOOP
       oper <= oper_tbl(i);
	   gval <= gval_tbl(i);
	   A <= '0'; B <= '0';
	   WAIT FOR 25 ns;
	   A <= '0'; B <= '1';
	   WAIT FOR 25 ns;
	   A <= '1'; B <= '0';
	   WAIT FOR 25 ns;
	   A <= '1'; B <= '1';
	   WAIT FOR 25 ns;
	END LOOP outter;
	WAIT;
  END PROCESS applytests;

END test;