LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.all; 
ENTITY tbregset IS
END tbregset;

ARCHITECTURE one OF tbregset IS
  --declare registers
  COMPONENT regset IS
    PORT (Abus,Bbus : OUT std_logic_vector (15 downto 0);
          Rbus : IN std_logic_vector (15 downto 0);
          ldrno,Arno,Brno : IN std_logic_vector (3 downto 0);
          ld,drvA,drvB : IN std_logic);
  END COMPONENT;
  FOR all : regset USE ENTITY work.regset(one);
  -- declare signals to hook up the register line
  SIGNAL Abus,Bbus,Rbus : std_logic_vector(15 downto 0);
  SIGNAL ldrno,Arno,Brno : std_logic_vector(3 downto 0) := "0000";
  SIGNAL ld,drvA,drvB : std_logic := '0';
  -- declare constants
  CONSTANT i0 : std_logic_vector (15 downto 0) := "0000000000000000";
  CONSTANT i1 : std_logic_vector (15 downto 0) := "1111111111111111";
  CONSTANT i2 : std_logic_vector (15 downto 0) := "1010101010101010";
  CONSTANT i3 : std_logic_vector (15 downto 0) := "0101010101010101";
  CONSTANT i4 : std_logic_vector (15 downto 0) := "1111000011110000";
  CONSTANT i5 : std_logic_vector (15 downto 0) := "0000001111111100";
  CONSTANT highz : std_logic_vector (15 downto 0) := "ZZZZZZZZZZZZZZZZ";
BEGIN
  rl : regset PORT MAP (Abus,Bbus,Rbus,ldrno,Arno,Brno,ld,drvA,drvB);
    
  PROCESS
  BEGIN
    WAIT for 10 ns;
    Rbus <= i0;
    WAIT for 10 ns;
    ld <= '1';
    WAIT for 30 ns;
    ld <= '0';
    Rbus <= highz;
    WAIT for 10 ns;
    drvA <= '1';
    WAIT for 10 ns;
    drvA <= '0';
    WAIT for 10 ns;
    drvB <= '1';
    WAIT for 10 ns;
    drvB <= '0';
    WAIT for 10 ns;
    Rbus <= i2;
    WAIT for 10 ns;
    ld <= '1';
    WAIT for 30 ns;
    ld <= '0';
    Rbus <= highz;
    WAIT for 10 ns;
    drvA <= '1';
    WAIT for 10 ns;
    drvA <= '0';
    WAIT for 10 ns;
    drvB <= '1';
    WAIT for 10 ns;
    drvB <= '0';
    WAIT for 10 ns;
    ldrno <= "1111"; Arno <= "1111"; Brno <= "1111";
    WAIT for 10 ns;
    Rbus <= i0;
    WAIT for 10 ns;
    ld <= '1';
    WAIT for 30 ns;
    ld <= '0';
    Rbus <= highz;
    WAIT for 10 ns;
    drvA <= '1';
    WAIT for 10 ns;
    drvA <= '0';
    WAIT for 10 ns;
    drvB <= '1';
    WAIT for 10 ns;
    drvB <= '0';
    WAIT for 10 ns;
    Rbus <= i2;
    WAIT for 10 ns;
    ld <= '1';
    WAIT for 30 ns;
    ld <= '0';
    Rbus <= highz;
    WAIT for 10 ns;
    drvA <= '1';
    WAIT for 10 ns;
    drvA <= '0';
    WAIT for 10 ns;
    drvB <= '1';
    WAIT for 10 ns;
    drvB <= '0';
    WAIT;
  END PROCESS;
END one;