-- this version of the test bench is to test the integration -- of the registers and the alu. See Semester Project a 9 -- This version includes instantiation of the register set. LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.all; USE WORK.dp430spt.all; ENTITY tbd IS END tbd; ARCHITECTURE one OF tbd IS --declare alu3 component --COMPONENT alu3 IS --PORT(A,B : IN std_logic_vector(15 downto 0); -- R : OUT std_logic_vector(15 downto 0); -- op : IN std_logic_vector(3 downto 0); -- loadA,loadB : IN std_logic; -- drive : IN std_logic; -- asub,Cin,s : IN std_logic; -- Cout,n,z : OUT std_logic); --END COMPONENT; --FOR all : alu3 USE ENTITY work.alu3(one); -- declare the register set COMPONENT regset IS PORT (Abus,Bbus : OUT std_logic_vector (15 downto 0); Rbus : IN std_logic_vector (15 downto 0); ldrno,Arno,Brno : IN std_logic_vector (3 downto 0); ld,drvA,drvB : IN std_logic); END COMPONENT; FOR all : regset USE ENTITY work.regset(one); -- declare constants for input stimulus CONSTANT i0 : std_logic_vector (15 downto 0) := "0000000000000000"; CONSTANT i1 : std_logic_vector (15 downto 0) := "1111111111111111"; CONSTANT i2 : std_logic_vector (15 downto 0) := "1010101010101010"; CONSTANT i3 : std_logic_vector (15 downto 0) := "0101010101010101"; CONSTANT i4 : std_logic_vector (15 downto 0) := "1111000011110000"; CONSTANT i5 : std_logic_vector (15 downto 0) := "0000001111111100"; CONSTANT r0 : std_logic_vector (15 downto 0) := "0000000000000000"; CONSTANT highz : std_logic_vector (15 downto 0) := "ZZZZZZZZZZZZZZZZ"; CONSTANT opand : std_logic_vector (3 downto 0) := "1000"; CONSTANT opor : std_logic_vector (3 downto 0) := "1110"; CONSTANT opxor : std_logic_vector (3 downto 0) := "0110"; CONSTANT opAbar : std_logic_vector (3 downto 0) := "0011"; CONSTANT op0 : std_logic_vector (3 downto 0) := "0000"; --CONSTANT regbin : array (15 downto 0) of std_logic_vector(3 downto 0) := -- ("1111","1110","1101","1100","1011","1010","1001","1000", -- "0111","0110","0101","0100","0011","0010","0001","1000"); -- declare signal to connect to DUT SIGNAL A,B,R : std_logic_vector(15 downto 0) := highz; SIGNAL op : std_logic_vector(3 downto 0) := "0000"; SIGNAL loadA,loadB,aludrive,asub,Cin,s,Cout,n,z : std_logic :='0'; SIGNAL ldrno,Arno,Brno : std_logic_vector(3 downto 0) := "0000"; SIGNAL rld,rdrvA,rdrvB : std_logic :='0'; -- declare enumeration types for making tesing easier TYPE busoptyp is (idle,drva,drvb,drvab,drvr,tbdra,tbdrb,tbdrvab,tbdrr, tblda,tbldb); TYPE aluctlintyp is (idle,ltca,ltcb,ltcab); TYPE aluopertpy is (aluopand,aluopor,aluopinv,aluopadd,aluopsub); BEGIN -- wire in the DUT -- d0 : alu3 PORT MAP (A,B,R,op,loadA,loadB,drive,asub,Cin,s,Cout,n,z); rs : regset PORT MAP (A,B,R,ldrno,Arno,Brno,rld,rdrvA,rdrvB); -- apply test and check PROCESS -- declare bus cycle signal generation and timing procedure -- modified in tbalu4 to include register control signals PROCEDURE buscycle (abusop,bbusop,rbusop : IN busoptyp; abusval,bbusval,rbusval : IN std_logic_vector(15 downto 0); aregno,bregno : integer; aluoper : IN aluopertpy) IS BEGIN WAIT FOR 10 ns; -- 10 ns into cycle CASE abusop IS WHEN tbdra => A <= abusval; WHEN drva => rdrvA <= '1'; Arno <= int2std4(aregno); WHEN OTHERS => null; END CASE; CASE bbusop IS WHEN tbdrb => B <= bbusval; WHEN drvb => rdrvB <= '1'; Brno <= int2std4(bregno); WHEN OTHERS => null; END CASE; --latch busses and apply control signals WAIT FOR 1 ns; -- 11 ns into cycle --CASE aluinctl IS -- WHEN ltcab => loadA <= '1'; loadb <= '1'; -- WHEN ltca => loadA <= '1'; -- WHEN ltcb => loadB <= '1'; -- WHEN idle => null; --END CASE; --op <= oper; --asub <= asub_v; --Cin <= Cin_v; --s <= s_v; WAIT FOR 39 ns; --50 ns into cycle A <= highz; B <= highz; rdrvA <= '0'; rdrvb <= '0'; loadA <= '0'; loadB <= '0'; -- advance to output driving WAIT FOR 25 ns; -- 75 ns into cycle -- n,z, and Cout are driven by the ALU unit CASE rbusop IS WHEN drvr => aludrive <= '1'; WHEN tbdrr => R <= rbusval; rld <= '1' after 1 ns; ldrno <= int2std4(aregno); WHEN others => null; END CASE; WAIT FOR 25 ns; R <= highz; rld <= '0'; aludrive <= '0'; END buscycle; BEGIN buscycle (idle,idle,tbdrr,i0,i0,i0,0,0,aluopand); buscycle (idle,idle,tbdrr,i0,i0,i1,1,0,aluopand); buscycle (drva,drvb,idle,i1,i1,i0,0,1,aluopand); buscycle (idle,idle,tbdrr,i0,i0,i0,2,0,aluopand); buscycle (idle,idle,tbdrr,i0,i0,i1,3,0,aluopand); buscycle (drva,drvb,idle,i1,i1,i0,2,3,aluopand); buscycle (idle,idle,tbdrr,i0,i0,i0,4,0,aluopand); buscycle (idle,idle,tbdrr,i0,i0,i1,5,0,aluopand); buscycle (drva,drvb,idle,i1,i1,i0,4,5,aluopand); buscycle (idle,idle,tbdrr,i0,i0,i0,6,0,aluopand); buscycle (idle,idle,tbdrr,i0,i0,i1,7,0,aluopand); buscycle (drva,drvb,idle,i1,i1,i0,6,7,aluopand); buscycle (idle,idle,tbdrr,i0,i0,i0,8,0,aluopand); buscycle (idle,idle,tbdrr,i0,i0,i1,9,0,aluopand); buscycle (drva,drvb,idle,i1,i1,i0,8,9,aluopand); buscycle (idle,idle,tbdrr,i0,i0,i0,10,0,aluopand); buscycle (idle,idle,tbdrr,i0,i0,i1,11,0,aluopand); buscycle (drva,drvb,idle,i1,i1,i0,10,11,aluopand); buscycle (idle,idle,tbdrr,i0,i0,i0,12,0,aluopand); buscycle (idle,idle,tbdrr,i0,i0,i1,13,0,aluopand); buscycle (drva,drvb,idle,i1,i1,i0,12,13,aluopand); buscycle (idle,idle,tbdrr,i0,i0,i0,14,0,aluopand); buscycle (idle,idle,tbdrr,i0,i0,i1,15,0,aluopand); buscycle (drva,drvb,idle,i1,i1,i0,14,15,aluopand); --buscycle (tbdra,tbdrb,drvr,i1,i1,i0,12,10,aluopand); --buscycle (tbdra,tbdrb,drvr,i1,i1,i0,12,10,aluopand); --buscycle (tbdra,tbdrb,i0,i1,ltca,opand,'0','0','0',rdrv,i0); --buscycle (tbdra,tbdrb,i0,i2,ltcb,opor,'0','0','0',rdrv,i0); --buscycle (tbdra,tbdrb,i0,i3,idle,opor,'0','0','0',rdrv,i0); --buscycle (tbdra,tbdrb,i3,i1,ltcab,opxor,'0','0','0',rdrv,i0); --buscycle (tbdra,tbdrb,i3,i1,ltcab,opxor,'0','0','1',rdrv,i0); --add more test to check your design -- buscycle (abusop,bbusop,abusval,bbusval,ALUloadctl,operation,asub,Cin,selectop,drive) -- values of parameters above WAIT; END PROCESS; END one;