ENTITY mux2_1x16 IS PORT (A,B : IN bit_vector (15 downto 0); S : IN bit; R : OUT bit_vector (15 downto 0)); END mux2_1x16; ARCHITECTURE one OF mux2_1x16 IS COMPONENT mux2_1 IS PORT (A,B : IN bit; S : IN bit; R : OUT bit); END COMPONENT; FOR all : mux2_1 USE ENTITY work.mux2_1(one); BEGIN u0 : mux2_1 PORT MAP (A(0),B(0),S,R(0)); u1 : mux2_1 PORT MAP (A(1),B(1),S,R(1)); u2 : mux2_1 PORT MAP (A(2),B(2),S,R(2)); u3 : mux2_1 PORT MAP (A(3),B(3),S,R(3)); u4 : mux2_1 PORT MAP (A(4),B(4),S,R(4)); u5 : mux2_1 PORT MAP (A(5),B(5),S,R(5)); u6 : mux2_1 PORT MAP (A(6),B(6),S,R(6)); u7 : mux2_1 PORT MAP (A(7),B(7),S,R(7)); u8 : mux2_1 PORT MAP (A(8),B(8),S,R(8)); u9 : mux2_1 PORT MAP (A(9),B(9),S,R(9)); u10 : mux2_1 PORT MAP (A(10),B(10),S,R(10)); u11 : mux2_1 PORT MAP (A(11),B(11),S,R(11)); u12 : mux2_1 PORT MAP (A(12),B(12),S,R(12)); u13 : mux2_1 PORT MAP (A(13),B(13),S,R(13)); u14 : mux2_1 PORT MAP (A(14),B(14),S,R(14)); u15 : mux2_1 PORT MAP (A(15),B(15),S,R(15)); END one; ARCHITECTURE two OF mux2_1x16 IS SIGNAL S16 : bit_vector (15 downto 0); BEGIN S16 <= S & S & S & S & S & S & S & S & S & S & S & S & S & S & S & S; R <= (A AND NOT S16) OR (B AND S16); END two;