LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.all;
ENTITY mbcpu IS
  PORT (dbus : INOUT STD_LOGIC_VECTOR (7 downto 0);
        dracc,bmuxltch : IN STD_LOGIC;
        aal,bbu,Ldac : IN STD_LOGIC;
        func : IN STD_LOGIC_VECTOR (3 downto 0);
        addsub,cin,arlo : IN STD_LOGIC;
        csel : IN STD_LOGIC_VECTOR (1 downto 0);
        cout,n,z : OUT STD_LOGIC);        
END mbcpu;

ARCHITECTURE one OF mbcpu IS
--COMPONENT declarations and configurations
--      (there are 4 different components)
-----
  
-----
  
-----
  
-----
  
--Local Declarations
CONSTANT zero : STD_LOGIC_VECTOR (7 downto 0) := "00000000";
SIGNAL bmuxout,blout,amux_acc,accout,alures : STD_LOGIC_VECTOR (7 downto 0);
--BIT version of hookup signals
SIGNAL accout_b,blout_b,r_b : BIT_VECTOR (7 downto 0);
SIGNAL cin_b,addsub_b,arlo_b,n_b,z_b,cout_b : BIT;
SIGNAL csel_b : BIT_VECTOR (1 downto 0);
SIGNAL func_b : BIT_VECTOR (3 downto 0);
------
BEGIN
  -- instantiate the components 


  -- the type conversions functions
  accout_b <= to_bitvector(accout,'0');
  blout_b <= to_bitvector(blout,'0');
  cin_b <= to_bit(cin,'0');
  addsub_b <= to_bit(addsub,'0');
  arlo_b <= to_bit(arlo,'0');
  csel_b <= to_bitvector(csel,'0');
  func_b <= to_bitvector(func,'0');
  alures <= to_StdLogicVector(r_b);
  cout <= to_StdULogic(cout_b);
  n <= to_StdULogic(n_b);
  z <= to_StdULogic(z_b);

END one;