-------------------------------------------------------------------------------
--  Test Bench Entity for the Register set
--   NEEDS modification for 3561 register set
-------------------------------------------------------------------------------
ENTITY  rtst IS
END rtst;

LIBRARY  IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ARCHITECTURE test OF rtst IS

COMPONENT reg_set_4 IS
  PORT ( ABUS,BBUS : INOUT std_logic_vector;
         Aload,Bload : IN  std_logic;
         Adrive,Bdrive : IN std_logic;
         AregNo,BregNo : IN std_logic_vector(1 downto 0));
END COMPONENT;
FOR ALL : reg_set_4 USE  ENTITY  WORK.reg_set_4(one);
  
SIGNAL  ABUS,BBUS : std_logic_vector (7 downto 0);
SIGNAL  Aload,Bload,Adrive,Bdrive : std_logic;
SIGNAL Aloadc,Bloadc,Adrivec,Bdrivec : std_logic;
SIGNAL  AregNo,BregNo : std_logic_vector(1 downto 0);
CONSTANT  HighZ : std_logic_vector (7 downto 0) := "ZZZZZZZZ";
TYPE   vals_type IS array (0 to 3) of std_logic_vector (7 downto 0);
CONSTANT  Vals  : vals_type := ("00000000","11111111",
          "01100110","10000001");
SIGNAL Abus_err, Bbus_err : BIT;
TYPE regno_type IS array (0 to 3) of std_logic_vector (1 downto 0);
CONSTANT regno : regno_type := ("00","01","10","11");

TYPE LDItype IS (Load,Drive,Idle); 

BEGIN

r0 : reg_set_4 PORT MAP (ABUS,BBUS,Aloadc,Bloadc,Adrivec,Bdrivec,AregNo,BregNo);

--check for signal polarity
Aloadc <= Aload;
Bloadc <= Bload;
Adrivec <= Adrive;
Bdrivec <= Bdrive;
------------------------------------------------------------------------
------------------------------------------------------------------------
applytest : PROCESS

------------------------------------------------------------------------
PROCEDURE applyNtest (A_ldi : LDItype; A_reg_no : std_logic_vector(1 downto 0);
                      A_BUS_VAL : std_logic_vector (7 downto 0);
                      A_BUS_EXP : std_logic_vector (7 downto 0);
                      B_ldi : LDItype; B_reg_no : std_logic_vector(1 downto 0);
                      B_BUS_VAL : std_logic_vector (7 downto 0);
                      B_BUS_EXP : std_logic_vector (7 downto 0)) IS
BEGIN
WAIT FOR 9 NS; --  9 ns into cycle
  IF (ABUS /= HighZ) THEN Abus_err <= '1','0' after 1 ns; END IF;
  IF (BBUS /= HighZ) THEN Bbus_err <= '1','0' after 1 ns; END IF;
WAIT FOR 1 NS; -- 10 ns into cycle
AregNo <= A_reg_no; BregNo <= B_reg_no;
WAIT FOR 1 NS;
CASE A_ldi IS
  WHEN Load  => Aload  <= '0'; ABUS <= A_BUS_VAL;
  WHEN Drive => Adrive <= '0'; 
  WHEN Idle  => null;
END CASE;
CASE B_ldi IS
  WHEN Load  => Bload  <= '0'; BBUS <= B_BUS_VAL;
  WHEN Drive => Bdrive <= '0'; 
  WHEN Idle  => null;
END CASE;
WAIT FOR 9 NS; -- 20 ns into cycle
  IF (ABUS /= A_BUS_EXP) THEN Abus_err <= '1','0' after 1 ns; END IF;
  IF (BBUS /= B_BUS_EXP) THEN Bbus_err <= '1','0' after 1 ns; END IF;
WAIT FOR 49 NS; -- 69 ns into cycle
  IF (ABUS /= A_BUS_EXP) THEN Abus_err <= '1','0' after 1 ns; END IF;
  IF (BBUS /= B_BUS_EXP) THEN Bbus_err <= '1','0' after 1 ns; END IF;
WAIT FOR  1 NS; -- 70 ns into cycle
IF (A_ldi = Load) THEN Aload <= '1'; END IF;
IF (B_ldi = Load) THEN Bload <= '1'; END IF;
WAIT FOR 10 NS; -- 80 ns into cycle
IF (A_ldi = Drive) THEN Adrive <= '1';
                   ELSE ABUS <= HighZ; END IF;
IF (B_ldi = Drive) THEN Bdrive <= '1';
                   ELSE BBUS <= HighZ; END IF;
WAIT FOR 11 NS; -- 91 ns into cycle
  IF (ABUS /= HighZ) THEN Abus_err <= '1','0' after 1 ns; END IF;
  IF (BBUS /= HighZ) THEN Bbus_err <= '1','0' after 1 ns; END IF;
WAIT FOR  9 NS; -- end of 100 ns cycle
END applyNtest;
------------------------------------------------------------------------

BEGIN
  ABUS <=  HighZ;  BBUS <= HighZ;
  AregNo <= regno(0);     BregNo <= regno(0);
  Aload  <= '1';   Bload  <= '1';
  Adrive <= '1';   Bdrive <= '1';
  --da1 <= vals(0); da2 <= vals(2); da3 <= vals(3); da4 <= vals(4);
  -------------------------------------------------------------------
  -- TEST LOADING AND READING VALUES ONE AT A TIME
  -------------------------------------------------------------------
  FOR I in 0 to 3 Loop
  -- load values into register I using A bus and redrive it on A bus
    FOR J in 0 to 3 LOOP
      applyNtest(load,regno(I),Vals(J),Vals(J),idle,regno(I),HighZ,HighZ);
      applyNtest(drive,regno(I),HighZ,Vals(J),idle,regno(I),HighZ,HighZ);
    END LOOP;
  -- drive last value input into register I onto B bus
    applyNtest(idle,regno(I),HighZ,HighZ,drive,regno(I),HighZ,Vals(3));
  -- load values into register I using B bus and redrive it on B bus
    FOR J in 0 to 3 LOOP
      applyNtest(idle,regno(I),HighZ,HighZ,load,regno(I),Vals(J),Vals(J));
      applyNtest(idle,regno(I),HighZ,HighZ,drive,regno(I),HighZ,Vals(J));
    END LOOP;
  -- drive last value onto A Bus
    applyNtest(drive,regno(I),HighZ,Vals(3),idle,regno(I),HighZ,HighZ);
  END Loop;
  -------------------------------------------------------------------
  -- TEST LOADING ONE REGISTER FROM A BUS AND ANOTHER FROM B BUS
  -------------------------------------------------------------------
  For I in 0 to 3 Loop
    applyNtest(load,regno(I),Vals(I),Vals(I),
               load,regno(3-I),Vals(3-I),Vals(3-I));
    applyNtest(drive,regno(I),HighZ,Vals(I),
               drive,regno(3-I),HighZ,Vals(3-I));
  END Loop;
  -------------------------------------------------------------------
  -- TEST LOADING ON ONE BUS AND DRIVING ON THE OTHER
  -------------------------------------------------------------------
  -- load a predetermined value in each register - testing of ABUS
  For I in 0 to 3 Loop
    applyNtest(load,regno(I),Vals(I),Vals(I),
               drive,regno(3-I),HighZ,Vals(3-I));
    applyNtest(drive,regno(I),HighZ,Vals(I),
               load,regno(3-I),Vals(3-I),Vals(3-I));
    applyNtest(idle,regno(I),HighZ,HighZ,
               drive,regno(3-I),HighZ,Vals(3-I));
  END Loop;
  -------------------------------------------------------------------
  WAIT;
END PROCESS;

END test;