ENTITY moore101 IS PORT (clk,x : IN bit; z : OUT bit); END moore101; ARCHITECTURE one OF moore101 IS TYPE state_type IS (s0,s1,s2,s3); SIGNAL state,next_state : state_type; BEGIN --state elements PROCESS BEGIN WAIT UNTIL clk='1' AND clk'event; state <= next_state; END PROCESS; --next state logic PROCESS (state,x) BEGIN CASE state IS WHEN s0 => IF (x='0') THEN next_state <= s0; ELSE next_state <= s1; END IF; WHEN s1 => IF (x='0') THEN next_state <= s2; ELSE next_state <= s1; END IF; WHEN s2 => IF (x='0') THEN next_state <= s0; ELSE next_state <= s3; END IF; WHEN s3 => IF (x='0') THEN next_state <= s2; ELSE next_state <= s1; END IF; END CASE; END PROCESS; --output logic - Moore machine PROCESS (state) BEGIN CASE state IS WHEN s0 => z <= '0'; WHEN s1 => z <= '0'; WHEN s2 => z <= '0'; WHEN s3 => z <= '1'; END CASE; END PROCESS; END one;