ENTITY mealy101 IS PORT (clk,x : IN bit; z : OUT bit); END mealy101; ARCHITECTURE one OF mealy101 IS TYPE state_type IS (s0,s1,s2); SIGNAL state,next_state : state_type; BEGIN --state elements mealy PROCESS BEGIN WAIT UNTIL clk='1' AND clk'event; state <= next_state; END PROCESS; --next state logic PROCESS (state,x) BEGIN CASE state IS WHEN s0 => IF (x='0') THEN next_state <= s0; ELSE next_state <= s1; END IF; WHEN s1 => IF (x='0') THEN next_state <= s2; ELSE next_state <= s1; END IF; WHEN s2 => IF (x='0') THEN next_state <= s0; ELSE next_state <= s1; END IF; END CASE; END PROCESS; -- output logic - mealy machine PROCESS (state,x) BEGIN CASE state IS WHEN s0 => z<='0'; WHEN s1 => z<='0'; WHEN s2 => IF (x='1') THEN z<='1'; ELSE z<= '0'; END IF; END CASE; END PROCESS; END one;