-- Name: entity gen is Port ( a : in BIT; b : in BIT; g0 : in BIT; g1 : in BIT; g2 : in BIT; g3 : in BIT; z : out BIT); end gen; architecture one of gen is begin Z <= (g0 AND NOT a AND NOT b) OR (g1 AND NOT a AND b) OR (g2 AND a AND NOT b) OR (g3 AND a AND b); end one;