-- This is the description of a 3 bit Gray Code counter.

ENTITY cnt3 IS
  PORT (clk : IN bit;
        cnt : OUT bit_vector(2 downto 0));
END cnt3;

ARCHITECTURE one OF cnt3 IS
  SIGNAL state,next_state : bit_vector(2 downto 0) := "000";
BEGIN
  -- Latching logic specification
  PROCESS
  BEGIN
    WAIT UNTIL clk='1' AND clk'event;
    state <= next_state;
  END PROCESS;
  
  --Next state logic for true logid
  PROCESS (state)
  BEGIN
    CASE state IS
    WHEN ("000") =>
      next_state <= "001";
    WHEN ("001") =>
      next_state <= "011";
    WHEN ("011") =>
      next_state <= "010";
    WHEN ("010") =>
      next_state <= "110";
    WHEN ("110") =>
      next_state <= "111";
    WHEN ("111") =>
      next_state <= "101";
    WHEN ("101") =>
      next_state <= "100";
    WHEN ("100") =>
      next_state <= "000";
    END CASE;
  END PROCESS;
  
  --Assign outputs
  cnt <= state;
  
END one;