-- This ENTITY/ARCH implements a clock divider and outputs
-- of each of the derived clocks.
-- Created:  8/17/2012
-- Creater/Copyright:  Joanne E. DeGroat
-- Description:  There is a single input, the base clock signal
--     clk.  The outputs are clkd2, the input clock divided by 2
--     or a clock at half the frequency.  Outputs are included
--     for the powers of 2 up to a clock divided by 256.
--

ENTITY clkdiv IS
  PORT (clk : IN bit;
        clkd2,clkd4,clkd8,clkd16,clkd32,clkd64,clk128,clk256 : OUT bit);
END clkdiv;

ARCHITECTURE one OF clkdiv IS
  SIGNAL c2,c4,c8,c16,c32,c64,c128,c256 : bit;
  SIGNAL f2,f4,f8,f16,f32,f64,f128,f256 : bit;
  COMPONENT DFF
    PORT (clk,D : IN bit;
          Q,Qbar : OUT bit);
  END COMPONENT;
  FOR ALL : DFF USE ENTITY work.dff(one);
  
BEGIN
  d2 : DFF PORT MAP(clk,f2,c2,f2);
  clkd2 <= c2;
  d4 : DFF PORT MAP(c2,f4,c4,f4);
  clkd4 <= c4;
  d8 : DFF PORT MAP(c4,f8,c8,f8);
  clkd8 <= c8;
  d16 : DFF PORT MAP(c8,f16,c16,f16);
  clkd16 <= c16;
  d32 : DFF PORT MAP(c16,f32,c32,f32);
  clkd32 <= c32;
  d64 : DFF PORT MAP(c32,f64,c64,f64);
  clkd64 <= c64;
  d128 : DFF PORT MAP (c64,f128,c128,f128);
  clk128 <= c128;
  d256 : DFF PORT MAP (c128,f256,c256,f256);
  clk256 <= c256;
END one;