ENTITY t_bird IS PORT (clk,lts,rtz,haz : IN bit; lc,lb,la,ra,rb,rc : OUT bit); END t_bird; ARCHITECTURE one OF t_bird IS TYPE state_type IS (idle,l1,l2,l3,r1,r2,r3,lr3); SIGNAL state,next_state : state_type; BEGIN --F/F process PROCESS BEGIN WAIT UNTIL (clk='1' AND clk'event); state <= next_state; END PROCESS; --next sate process PROCESS (state,ltr,rts,haz) BEGIN CASE state IS WHEN idle => IF (haz='1' OR (lts='1' AND rts='1') THEN next_state <= lr3; ELSIF (haz='0' OR (lts='0' AND rts='1') THEN next_state <= r1; ELSIF (haz='0' OR (lts='1' AND rts='0') THEN next_state <= l1; ELSE next_state <= idle; END IF; WHEN l1 => IF (haz='1') THEN next_state <= lr3; ELSE next_state <= l2; END IF; WHEN l2 => IF (haz='1') THEN next_state <= lr3; ELSE next_state <= l3; END IF; WHEN l3 => next_state <= idle; WHEN r1 => IF (haz='1') THEN next_state <= lr3; ELSE next_state <= r2; END IF; WHEN r2 => IF (haz='1') THEN next_state <= lr3; ELSE next_state <= r3; END IF; WHEN r3 => next_state <= idle; WHEN lr3 => next_state <= idle; END CASE; END PROCESS; --output process PROCESS (state) BEGIN CASE state IS WHEN idle => lc <= '0'; lb <= '0'; la <= '0'; ra <= '0'; rb <= '0'; rc <= '0'; WHEN l1 => lc <= '0'; lb <= '0'; la <= '1'; ra <= '0'; rb <= '0'; rc <= '0'; WHEN l2 => lc <= '0'; lb <= '1'; la <= '1'; ra <= '0'; rb <= '0'; rc <= '0'; WHEN l3 => lc <= '1'; lb <= '1'; la <= '1'; ra <= '0'; rb <= '0'; rc <= '0'; WHEN r1 => lc <= '0'; lb <= '0'; la <= '0'; ra <= '1'; rb <= '0'; rc <= '0'; WHEN r2 => lc <= '0'; lb <= '0'; la <= '0'; ra <= '1'; rb <= '1'; rc <= '0'; WHEN r3 => lc <= '0'; lb <= '0'; la <= '0'; ra <= '1'; rb <= '1'; rc <= '1'; WHEN lr3 => lc <= '1'; lb <= '1'; la <= '1'; ra <= '1'; rb <= '1'; rc <= '1'; END PROCESS; END one;