ENTITY e3_bcd IS PORT (clk,e3in : IN bit; bcdout : OUT bit); END e3_bcd; ARCHITECTURE one OF e3_bcd IS SIGNAL state,next_state : bit_vector(2 downto 0); BEGIN -- Latching logic specification PROCESS BEGIN WAIT UNTIL clk='1' AND clk'event; state <= next_state; END PROCESS; --Next State Logic (ref sl 14) PROCESS (state) BEGIN CASE state IS WHEN ("000") => IF (e3in = '0') THEN next_state <= "100"; ELSE next_state <= "101"; END IF; WHEN ("100") => IF (e3in = '0') THEN next_state <= "111"; ELSE next_state <= "110"; END IF; WHEN ("101") => IF (e3in = '0') THEN next_state <= "110"; ELSE next_state <= "110"; END IF; WHEN ("111") --this is for you to complete END CASE; END PROCESS; --Assignment of output PROCESS (state) BEGIN CASE state IS WHEN ("000") => IF (e3in = '0') THEN bcdout <= '1'; ELSE bcdout <= '0'; END IF; WHEN ("100") => IF (e3in = '0') THEN bcdout <= '1'; ELSE bcdout <= '0'; END IF; WHEN ("101") => IF (e3in = '0') THEN bcdout <= '0'; ELSE bcdout <= '1'; END IF; WHEN ("111") --this is for you to complete END CASE; END PROCESS; END one;