----------------------------------------------------------------
-- The ENTITY of the counter
----------------------------------------------------------------
ENTITY cnt3 IS
  PORT (clk : IN bit;
        cnt : OUT bit_vector (2 downto 0));
END cnt3;
----------------------------------------------------------------
-- completee this architecture
ARCHITECTURE mysymbolic OF cnt3 IS

BEGIN

END mysymbolic;
----------------------------------------------------------------
-- completee this architecture
ARCHITECTURE mybinary OF cnt3 IS

BEGIN

END mybinary;
----------------------------------------------------------------
-- The Testbench
ENTITY vass3 IS
END vass3;

ARCHITECTURE one OF vass3 IS
   
   --declaration for 3 bit counter
   COMPONENT cnt3 IS
      PORT (clk : IN bit;
            cnt : OUT bit_vector(2 downto 0) );
   END COMPONENT;
   -- configurations for both architectures
   

   -- signals 
   SIGNAL clk : BIT;

   SIGNAL cntsym,cntbin : bit_vector (2 downto 0);
     
BEGIN
  -- Instantiage your architectures here


  -- Clock generation
   PROCESS  --Generate a 20 MHz clock signal 50% duty cycle
   BEGIN
     clk <= NOT clk;
     WAIT FOR 20 ns;
     clk <= NOT clk;
     WAIT FOR 20 ns;
   END PROCESS;
     
END one;