------------------------------------------------------------------
-- Sequence 010 and 1001 detector  - VHDL ENTITY
------------------------------------------------------------------
ENTITY vass2 IS
  PORT (x : IN bit;
        clk : IN bit;
        z : OUT bit);
END vass2;
------------------------------------------------------------------
-- Sequence 010 and 1001 detector - VHDL Architecture
------------------------------------------------------------------
ARCHITECTURE one OF vass2 IS
  -- enter your declaration for the state type and state signals

BEGIN
-- enter your sequential machine architecture description here
-- F/F Process

-- Next State Process

-- Output Process

END one;
------------------------------------------------------------------
-- TESTBENCH
------------------------------------------------------------------
ENTITY tb2 IS
END tb2;

ARCHITECTURE one OF tb2 IS
  -- Component declaration and configuration
  COMPONENT vass2 IS
  PORT (x : IN bit;
        clk : IN bit;
        z : OUT bit);
  END COMPONENT;
  FOR all : vass2 USE ENTITY work.vass2(one);
  -- delcare signals needed in the testbench
  --TYPE x_seq_type IS bit_vector(0 to 32);
  SIGNAL x_seq : bit_vector(0 to 32) := "000100001001001000100100010010110";
  SIGNAL clk,xin,z : bit;
  
  
BEGIN
  -- component instantiation -  THE DUT
  u0 : vass2 PORT MAP (xin,clk,z);
  
  ----------------------------------------
  -- the clock  
  clk <= not clk after 10 ns;
  ----------------------------------------

  PROCESS
  BEGIN
    WAIT FOR 5 ns;
    FOR i IN 0 to 32 LOOP
      xin <=  x_seq(i);
      WAIT FOR 20 ns;
    END LOOP;
    -- done applying sequence of x inputs
    WAIT FOR 40 ns;
    WAIT;
  END PROCESS;
END one;