LIBRARY IEEE; USE IEEE.std_logic_1164.all; ENTITY tdp IS END tdp; ARCHITECTURE one OF tdp IS -- declare DUT COMPONENT mbdp IS PORT (dbus : INOUT std_logic_vector(7 downto 0); addsub,cin,arlo : IN std_logic; csel : IN std_logic_vector(1 downto 0); fun : IN std_logic_vector(3 downto 0); cout,nflag,zflag : OUT std_logic; bmuxlatch,aal,bbu,ldac,dracc : IN std_logic); END COMPONENT; FOR all : mbdp USE ENTITY work.mbdp(one); -- declare hookup signals SIGNAL dbus : std_logic_vector(7 downto 0); SIGNAL addsub,cin,arlo,cout,nflag,zflag : std_logic; SIGNAL csel : std_logic_vector(1 downto 0); SIGNAL fun : std_logic_vector(3 downto 0); SIGNAL bmuxlatch,aal,bbu,ldacc,dracc : std_logic; BEGIN -- hook up DUT u0 : mbdp PORT MAP (dbus,addsub,cin,arlo,csel,fun,cout,nflag,zflag,bmuxlatch,aal,bbu,ldacc,dracc); -- stimulus PROCESS PROCESS BEGIN -- TEST LOADING THE ACCUMULATOR --CYC ST -- set up intiail vectors and control signals - this cycle load accumulator and the blatch with 0 dbus <= "ZZZZZZZZ"; addsub <= '0'; cin <= '0'; arlo <= '1'; csel <= "10"; fun <= "1110"; bmuxlatch <= '0'; aal <= '0'; bbu <= '0'; ldacc <= '0'; dracc <= '0'; WAIT FOR 10 ns; dbus <= "10101010"; aal <= '1'; bmuxlatch <= '1'; WAIT FOR 10 ns; ldacc <= '1'; WAIT FOR 60 ns; dbus <= "ZZZZZZZZ"; aal <= '0'; ldacc <= '0'; bmuxlatch <= '0'; WAIT FOR 20 ns; -- --CYC ST -- set up intiail vectors and control signals - this cycle drive the accumulator onto the bus dbus <= "ZZZZZZZZ"; addsub <= '0'; cin <= '0'; arlo <= '1'; csel <= "10"; fun <= "1110"; bmuxlatch <= '0'; aal <= '0'; bbu <= '0'; ldacc <= '0'; dracc <= '0'; WAIT FOR 10 ns; dracc <= '1'; aal <= '1'; bmuxlatch <= '1'; WAIT FOR 10 ns; -- ldacc <= '1'; WAIT FOR 60 ns; dbus <= "ZZZZZZZZ"; dracc <= '0'; aal <= '0'; ldacc <= '0'; bmuxlatch <= '0'; WAIT FOR 20 ns; -- --CYC ST -- set up intiail vectors and control signals - this cycle adds a b input of 00001111 to the acc dbus <= "ZZZZZZZZ"; addsub <= '0'; cin <= '0'; arlo <= '1'; csel <= "10"; fun <= "1110"; bmuxlatch <= '0'; aal <= '0'; bbu <= '0'; ldacc <= '0'; dracc <= '0'; WAIT FOR 10 ns; dbus <= "00001111"; bbu <= '1'; WAIT FOR 10 ns; bmuxlatch <= '1'; -- ldacc <= '1'; WAIT FOR 60 ns; dbus <= "ZZZZZZZZ"; dracc <= '0'; aal <= '0'; ldacc <= '1', '0' after 10 ns; bmuxlatch <= '0'; WAIT FOR 20 ns; -- --CYC ST -- set up intiail vectors and control signals - this cycle drive the accumulator onto the bus dbus <= "ZZZZZZZZ"; addsub <= '0'; cin <= '0'; arlo <= '1'; csel <= "10"; fun <= "1110"; bmuxlatch <= '0'; aal <= '0'; bbu <= '0'; ldacc <= '0'; dracc <= '0'; WAIT FOR 10 ns; dracc <= '1'; aal <= '1'; bmuxlatch <= '1'; WAIT FOR 10 ns; -- ldacc <= '1'; WAIT FOR 60 ns; dbus <= "ZZZZZZZZ"; dracc <= '0'; aal <= '0'; ldacc <= '0'; bmuxlatch <= '0'; WAIT FOR 20 ns; -- --CYC ST -- set up intiail vectors and control signals - this cycle is a logical a OR b input of 00001111 to the acc dbus <= "ZZZZZZZZ"; addsub <= '0'; cin <= '0'; arlo <= '0'; csel <= "10"; fun <= "1110"; bmuxlatch <= '0'; aal <= '0'; bbu <= '0'; ldacc <= '0'; dracc <= '0'; WAIT FOR 10 ns; dbus <= "00001111"; bbu <= '1'; WAIT FOR 10 ns; bmuxlatch <= '1'; -- ldacc <= '1'; WAIT FOR 60 ns; dbus <= "ZZZZZZZZ"; dracc <= '0'; aal <= '0'; ldacc <= '1', '0' after 10 ns; bmuxlatch <= '0'; WAIT FOR 20 ns; -- --CYC ST -- set up intiail vectors and control signals - this cycle drive the accumulator onto the bus dbus <= "ZZZZZZZZ"; addsub <= '0'; cin <= '0'; arlo <= '1'; csel <= "10"; fun <= "1110"; bmuxlatch <= '0'; aal <= '0'; bbu <= '0'; ldacc <= '0'; dracc <= '0'; WAIT FOR 10 ns; dracc <= '1'; aal <= '1'; bmuxlatch <= '1'; WAIT FOR 10 ns; -- ldacc <= '1'; WAIT FOR 60 ns; dbus <= "ZZZZZZZZ"; dracc <= '0'; aal <= '0'; ldacc <= '0'; bmuxlatch <= '0'; WAIT FOR 20 ns; WAIT FOR 100 ns; WAIT; END PROCESS; END one;