LIBRARY IEEE; USE IEEE.std_logic_1164.all; ENTITY csa16 IS PORT (A,B : IN std_logic_vector (15 downto 0); Cin : IN std_logic; SUM : OUT std_logic_vector (15 downto 0); Cout : OUT std_logic); END csa16; ARCHITECTURE one OF csa16 IS COMPONENT add4 IS PORT (A,B : IN std_logic_vector (3 downto 0); Cin : IN std_logic; SUM : OUT std_logic_vector (3 downto 0); Cout : OUT std_logic); END COMPONENT; FOR all : add4 USE ENTITY work.add4(one); COMPONENT add4p0 IS PORT (A,B : IN std_logic_vector (3 downto 0); SUM : OUT std_logic_vector (3 downto 0); Cout : OUT std_logic); END COMPONENT; FOR all : add4p0 USE ENTITY work.add4p0(one); COMPONENT add4p1 IS PORT (A,B : IN std_logic_vector (3 downto 0); SUM : OUT std_logic_vector (3 downto 0); Cout : OUT std_logic); END COMPONENT; FOR all : add4p1 USE ENTITY work.add4p1(one); COMPONENT mux2t1x4 IS PORT (A,B : IN std_logic_vector(3 downto 0); sel : In std_logic; Mout : OUT std_logic_vector(3 downto 0)); END COMPONENT; FOR all : mux2t1x4 USE ENTITY work.mux2t1x4(one); -- local signals SIGNAL sump02,sump12,sump03,sump13,sump04,sump14 : std_logic_vector (3 downto 0); SIGNAL cint,cp02,cp12,cp03,cp13,cp04,cp14,c2out,c3out : std_logic; BEGIN -- component instantiations a1 : add4 PORT MAP (A(3 downto 0),B(3 downto 0),Cin,SUM(3 downto 0),cint); a2p0 : add4p0 PORT MAP (A(7 downto 4),B(7 downto 4),sump02,cp02); a2p1 : add4p1 PORT MAP (A(7 downto 4),B(7 downto 4),sump12,cp12); mux2 : mux2t1x4 PORT MAP (sump02,sump12,cint,SUM(7 downto 4)); c2out <= cp02 WHEN cint='0' ELSE cp12; a3p0 : add4p0 PORT MAP (A(11 downto 8),B(11 downto 8),sump03,cp03); a3p1 : add4p1 PORT MAP (A(11 downto 8),B(11 downto 8),sump13,cp13); mux3 : mux2t1x4 PORT MAP (sump03,sump13,c2out,SUM(11 downto 8)); c3out <= cp03 WHEN c2out='0' ELSE cp13; a4p0 : add4p0 PORT MAP (A(15 downto 12),B(15 downto 12),sump04,cp04); a4p1 : add4p1 PORT MAP (A(15 downto 12),B(15 downto 12),sump14,cp14); mux4 : mux2t1x4 PORT MAP (sump04,sump14,c3out,SUM(15 downto 12)); Cout <= cp04 WHEN c3out='0' ELSE cp14; END one;