ABSTRACT: This report presents design and implementation of experimental test-bed for three-phase 5 kVA On-line UPS system. The test-bed consists of a three-phase PWM rectifier, DC bus tank, a three-phase PWM inverter, L-C output filter, a D/Y transformer, and a 3-phase load. A discrete-time state space model of the plant is given and two discrete-time controllers are proposed to perform zero steady-state tracking error, THD reduction, and fast and no-overshoot response: a discrete-time sliding-mode current controller (DSMC) in the inner loop and a discrete-time robust servomechanism problem (RSP) voltage controller in the outer loop. To validate the effectiveness of the analyzed circuit model and control strategies, various simulation results using Matlab/Simulink are presented under linear and nonlinear loads, and all Matlab/Simulink codes are included in this report. A real test-bed for 5 kVA On-line UPS system is built to show experimental results using TI DSP TMS320LF2407. Moreover, all interface circuits with DSP and all source codes such as C language and assembly language files needed for DSP implementation are given in Appendix. Therefore, this report can give help to people who want to learn how to design voltage/current controllers, construct a simulation test-bed using Matlab/Simulink, set-up DSP interface board, and build a real test-bed using power converter and DSP.
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